Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
>
> > +static void gen12_init_reg_state(u32 * const regs,
> > + struct intel_context *ce,
> > + struct intel_engine_cs *engine,
> > + struct intel_ring *ring)
> > +{
> > + struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(ce->vm);
> > + const bool rcs = engine->class == RENDER_CLASS;
> > + const u32 base = engine->mmio_base;
> > + const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
> > + MI_LRI_CS_MMIO : 0;
> > +
> > + GEM_DEBUG_EXEC(DRM_INFO_ONCE("Using GEN12 Register State Context\n"));
> > +
> > + regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 11 : 9) |
>
> I would've kept a constant 13 here since we'll need to set the 13th
> register (that's the semaphore reg you had in the previous revision),
> but anyway we can bump it when that support is added in.
I left this for a future task. Early next week I hope to have a new
selftest ready that enforces that our init_reg_state() matches the HW
layout. For now, this gets us onto the next error we need to debug.
Thanks for the patches and reviewing,
-Chris
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