On Fri, Sep 06, 2019 at 02:36:49PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> > Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> > TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> > during some power state transitions.
> >
> > Bspec: 49201
> > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 76f11d465e91..d3e56628af70 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1855,8 +1855,6 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > u32 val;
> > int div;
> >
> > - cdclk_state->bypass = 50000;
> > -
> > val = I915_READ(SKL_DSSM);
> > switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > default:
> > @@ -1873,6 +1871,11 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > break;
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + cdclk_state->bypass = cdclk_state->ref / 2;
> > + else
> > + cdclk_state->bypass = 50000;
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> PS. I'd still like to see a icl_cdclk_pll_update() so I wouldn't have to
> scratch my head why this looks so different to bxt/cnl code.
Applied to dinq; thanks for the review. As you mentioned, I'll look
into further updates to the ICL-style cdclk code to bring it more in
line with other platforms.
Matt
>
> > +
> > val = I915_READ(BXT_DE_PLL_ENABLE);
> > if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > (val & BXT_DE_PLL_LOCK) == 0) {
> > --
> > 2.20.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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