Re: [PATCH] drm/i915: Convert ICL-style DSI to use phy namespace

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On Wed, 04 Sep 2019, Matt Roper <matthew.d.roper@xxxxxxxxx> wrote:
> ICL+ DSI outputs operate a bit differently than DP/HDMI/eDP and are more
> closely tied to the PHY than to the DDI.  Since we've separated PHY's
> out into their own namespace it makes sense to operate on 'enum phy'
> throughout most of the ICL DSI code rather than 'enum port' which we
> generally use to refer to the DDI these days.  Part of this transition
> has already been done as part of commit dc867bc7d887 ("drm/i915/gen11:
> Convert combo PHY logic to use new 'enum phy' namespace"), although that
> patch only migrated the parts of the code that were specifically
> updating the combo PHY registers themselves.  Moving the rest of the
> code over to the PHY namespace as well will hopefully make things more
> consistent and less confusing.
>
> Note that the change here is really just a naming change.  On all of the
> platforms that this code currently applies to, the DSI outputs always
> have port==phy so we're still passing the same integer values around no
> matter which type of enum they belong to..
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>

Cc: Ville & Vandita, FYI, maybe you want to eyeball through this.

Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c   | 236 ++++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_dsi.h |   5 +-
>  2 files changed, 126 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..5cf32032e795 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -65,9 +65,9 @@ static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
>  		DRM_ERROR("DSI payload credits not released\n");
>  }
>  
> -static enum transcoder dsi_port_to_transcoder(enum port port)
> +static enum transcoder dsi_phy_to_transcoder(enum phy phy)
>  {
> -	if (port == PORT_A)
> +	if (phy == PHY_A)
>  		return TRANSCODER_DSI_0;
>  	else
>  		return TRANSCODER_DSI_1;
> @@ -78,20 +78,20 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	struct mipi_dsi_device *dsi;
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	int ret;
>  
>  	/* wait for header/payload credits to be released */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		wait_for_header_credits(dev_priv, dsi_trans);
>  		wait_for_payload_credits(dev_priv, dsi_trans);
>  	}
>  
>  	/* send nop DCS command */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi = intel_dsi->dsi_hosts[port]->device;
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi = intel_dsi->dsi_hosts[phy]->device;
>  		dsi->mode_flags |= MIPI_DSI_MODE_LPM;
>  		dsi->channel = 0;
>  		ret = mipi_dsi_dcs_nop(dsi);
> @@ -100,14 +100,14 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
>  	}
>  
>  	/* wait for header credits to be released */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		wait_for_header_credits(dev_priv, dsi_trans);
>  	}
>  
>  	/* wait for LP TX in progress bit to be cleared */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
>  				  LPTX_IN_PROGRESS), 20))
>  			DRM_ERROR("LPTX bit not cleared\n");
> @@ -119,7 +119,7 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
>  {
>  	struct intel_dsi *intel_dsi = host->intel_dsi;
>  	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> -	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> +	enum transcoder dsi_trans = dsi_phy_to_transcoder(host->phy);
>  	int free_credits;
>  	int i, j;
>  
> @@ -146,7 +146,7 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
>  {
>  	struct intel_dsi *intel_dsi = host->intel_dsi;
>  	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> -	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> +	enum transcoder dsi_trans = dsi_phy_to_transcoder(host->phy);
>  	u32 tmp;
>  	int free_credits;
>  
> @@ -305,7 +305,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>  	u32 afe_clk_khz; /* 8X Clock */
>  	u32 esc_clk_div_m;
> @@ -315,29 +315,29 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>  
>  	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		I915_WRITE(ICL_DSI_ESC_CLK_DIV(phy),
>  			   esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
> -		POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
> +		POSTING_READ(ICL_DSI_ESC_CLK_DIV(phy));
>  	}
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(phy),
>  			   esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
> -		POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
> +		POSTING_READ(ICL_DPHY_ESC_CLK_DIV(phy));
>  	}
>  }
>  
>  static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
>  				     struct intel_dsi *intel_dsi)
>  {
> -	enum port port;
> +	enum phy phy;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		WARN_ON(intel_dsi->io_wakeref[port]);
> -		intel_dsi->io_wakeref[port] =
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		WARN_ON(intel_dsi->io_wakeref[phy]);
> +		intel_dsi->io_wakeref[phy] =
>  			intel_display_power_get(dev_priv,
> -						port == PORT_A ?
> +						phy == PHY_A ?
>  						POWER_DOMAIN_PORT_DDI_A_IO :
>  						POWER_DOMAIN_PORT_DDI_B_IO);
>  	}
> @@ -347,13 +347,13 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	u32 tmp;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		tmp = I915_READ(ICL_DSI_IO_MODECTL(phy));
>  		tmp |= COMBO_PHY_MODE_DSI;
> -		I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
> +		I915_WRITE(ICL_DSI_IO_MODECTL(phy), tmp);
>  	}
>  
>  	get_dsi_io_power_domains(dev_priv, intel_dsi);
> @@ -476,17 +476,24 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 tmp;
> -	enum port port;
> +	enum phy phy;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp = I915_READ(DDI_BUF_CTL(port));
> +	/*
> +	 * Take note: although we usually use 'port' to refer to the DDI on
> +	 * platforms where the DDI is distinct from the PHY, it's still safe to
> +	 * use the phy index here.  The only platform that has port != phy
> +	 * situations is EHL and DSI on PHY-A there always uses DDI-A, never
> +	 * DDI-D.
> +	 */
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		tmp = I915_READ(DDI_BUF_CTL(phy));
>  		tmp |= DDI_BUF_CTL_ENABLE;
> -		I915_WRITE(DDI_BUF_CTL(port), tmp);
> +		I915_WRITE(DDI_BUF_CTL(phy), tmp);
>  
> -		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
> +		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(phy)) &
>  				  DDI_BUF_IS_IDLE),
>  				  500))
> -			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
> +			DRM_ERROR("DDI port:%c buffer idle\n", phy_name(phy));
>  	}
>  }
>  
> @@ -495,32 +502,31 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 tmp;
> -	enum port port;
>  	enum phy phy;
>  
>  	/* Program T-INIT master registers */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(phy));
>  		tmp &= ~MASTER_INIT_TIMER_MASK;
>  		tmp |= intel_dsi->init_count;
> -		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
> +		I915_WRITE(ICL_DSI_T_INIT_MASTER(phy), tmp);
>  	}
>  
>  	/* Program DPHY clock lanes timings */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		I915_WRITE(DPHY_CLK_TIMING_PARAM(phy), intel_dsi->dphy_reg);
>  
>  		/* shadow register inside display core */
> -		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +		I915_WRITE(DSI_CLK_TIMING_PARAM(phy), intel_dsi->dphy_reg);
>  	}
>  
>  	/* Program DPHY data lanes timings */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		I915_WRITE(DPHY_DATA_TIMING_PARAM(phy),
>  			   intel_dsi->dphy_data_lane_reg);
>  
>  		/* shadow register inside display core */
> -		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> +		I915_WRITE(DSI_DATA_TIMING_PARAM(phy),
>  			   intel_dsi->dphy_data_lane_reg);
>  	}
>  
> @@ -532,17 +538,17 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>  	 */
>  	if (IS_GEN(dev_priv, 11)) {
>  		if (intel_dsi_bitrate(intel_dsi) <= 800000) {
> -			for_each_dsi_port(port, intel_dsi->ports) {
> -				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
> +			for_each_dsi_phy(phy, intel_dsi->phys) {
> +				tmp = I915_READ(DPHY_TA_TIMING_PARAM(phy));
>  				tmp &= ~TA_SURE_MASK;
>  				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
> -				I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
> +				I915_WRITE(DPHY_TA_TIMING_PARAM(phy), tmp);
>  
>  				/* shadow register inside display core */
> -				tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
> +				tmp = I915_READ(DSI_TA_TIMING_PARAM(phy));
>  				tmp &= ~TA_SURE_MASK;
>  				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
> -				I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> +				I915_WRITE(DSI_TA_TIMING_PARAM(phy), tmp);
>  			}
>  		}
>  	}
> @@ -628,11 +634,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
>  	enum pipe pipe = intel_crtc->pipe;
>  	u32 tmp;
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
>  
>  		if (intel_dsi->eotp_pkt)
> @@ -711,8 +717,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  
>  	/* enable port sync mode if dual link */
>  	if (intel_dsi->dual_link) {
> -		for_each_dsi_port(port, intel_dsi->ports) {
> -			dsi_trans = dsi_port_to_transcoder(port);
> +		for_each_dsi_phy(phy, intel_dsi->phys) {
> +			dsi_trans = dsi_phy_to_transcoder(phy);
>  			tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
>  			tmp |= PORT_SYNC_MODE_ENABLE;
>  			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
> @@ -722,8 +728,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  		configure_dual_link_mode(encoder, pipe_config);
>  	}
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  
>  		/* select data lane width */
>  		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> @@ -753,8 +759,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  	}
>  
>  	/* wait for link ready */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
>  				LINK_READY), 2500))
>  			DRM_ERROR("DSI link not ready\n");
> @@ -769,7 +775,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	const struct drm_display_mode *adjusted_mode =
>  					&pipe_config->base.adjusted_mode;
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	/* horizontal timings */
>  	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
> @@ -806,8 +812,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  		DRM_ERROR("hactive pixels are not multiple of 4\n");
>  
>  	/* program TRANS_HTOTAL register */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		I915_WRITE(HTOTAL(dsi_trans),
>  			   (hactive - 1) | ((htotal - 1) << 16));
>  	}
> @@ -829,16 +835,16 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  			hsync_end /= 2;
>  		}
>  
> -		for_each_dsi_port(port, intel_dsi->ports) {
> -			dsi_trans = dsi_port_to_transcoder(port);
> +		for_each_dsi_phy(phy, intel_dsi->phys) {
> +			dsi_trans = dsi_phy_to_transcoder(phy);
>  			I915_WRITE(HSYNC(dsi_trans),
>  				   (hsync_start - 1) | ((hsync_end - 1) << 16));
>  		}
>  	}
>  
>  	/* program TRANS_VTOTAL register */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		/*
>  		 * FIXME: Programing this by assuming progressive mode, since
>  		 * non-interlaced info from VBT is not saved inside
> @@ -856,8 +862,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  		DRM_ERROR("vsync_start less than vactive\n");
>  
>  	/* program TRANS_VSYNC register */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		I915_WRITE(VSYNC(dsi_trans),
>  			   (vsync_start - 1) | ((vsync_end - 1) << 16));
>  	}
> @@ -868,15 +874,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	 * info available as described above.
>  	 * program TRANS_VSYNCSHIFT register
>  	 */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
>  	}
>  
>  	/* program TRANS_VBLANK register, should be same as vtotal programmed */
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		for_each_dsi_port(port, intel_dsi->ports) {
> -			dsi_trans = dsi_port_to_transcoder(port);
> +		for_each_dsi_phy(phy, intel_dsi->phys) {
> +			dsi_trans = dsi_phy_to_transcoder(phy);
>  			I915_WRITE(VBLANK(dsi_trans),
>  				   (vactive - 1) | ((vtotal - 1) << 16));
>  		}
> @@ -887,12 +893,12 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		tmp = I915_READ(PIPECONF(dsi_trans));
>  		tmp |= PIPECONF_ENABLE;
>  		I915_WRITE(PIPECONF(dsi_trans), tmp);
> @@ -908,7 +914,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
>  
> @@ -926,8 +932,8 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>  	lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
>  	ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  
>  		/* program hst_tx_timeout */
>  		tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
> @@ -990,14 +996,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	struct mipi_dsi_device *dsi;
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  	int ret;
>  
>  	/* set maximum return packet size */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  
>  		/*
>  		 * FIXME: This uses the number of DW's currently in the payload
> @@ -1007,7 +1013,7 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>  		tmp &= NUMBER_RX_PLOAD_DW_MASK;
>  		/* multiply "Number Rx Payload DW" by 4 to get max value */
>  		tmp = tmp * 4;
> -		dsi = intel_dsi->dsi_hosts[port]->device;
> +		dsi = intel_dsi->dsi_hosts[phy]->device;
>  		ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
>  		if (ret < 0)
>  			DRM_ERROR("error setting max return pkt size%d\n", tmp);
> @@ -1065,12 +1071,12 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  
>  		/* disable transcoder */
>  		tmp = I915_READ(PIPECONF(dsi_trans));
> @@ -1100,13 +1106,13 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  
>  	/* put dsi link in ULPS */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		tmp = I915_READ(DSI_LP_MSG(dsi_trans));
>  		tmp |= LINK_ENTER_ULPS;
>  		tmp &= ~LINK_ULPS_TYPE_LP11;
> @@ -1119,8 +1125,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  	}
>  
>  	/* disable ddi function */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
>  		tmp &= ~TRANS_DDI_FUNC_ENABLE;
>  		I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
> @@ -1128,8 +1134,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  
>  	/* disable port sync mode if dual link */
>  	if (intel_dsi->dual_link) {
> -		for_each_dsi_port(port, intel_dsi->ports) {
> -			dsi_trans = dsi_port_to_transcoder(port);
> +		for_each_dsi_phy(phy, intel_dsi->phys) {
> +			dsi_trans = dsi_phy_to_transcoder(phy);
>  			tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
>  			tmp &= ~PORT_SYNC_MODE_ENABLE;
>  			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
> @@ -1142,19 +1148,19 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 tmp;
> -	enum port port;
> +	enum phy phy;
>  
>  	gen11_dsi_ungate_clocks(encoder);
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp = I915_READ(DDI_BUF_CTL(port));
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		tmp = I915_READ(DDI_BUF_CTL(phy));
>  		tmp &= ~DDI_BUF_CTL_ENABLE;
> -		I915_WRITE(DDI_BUF_CTL(port), tmp);
> +		I915_WRITE(DDI_BUF_CTL(phy), tmp);
>  
> -		if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
> +		if (wait_for_us((I915_READ(DDI_BUF_CTL(phy)) &
>  				 DDI_BUF_IS_IDLE),
>  				 8))
>  			DRM_ERROR("DDI port:%c buffer not idle\n",
> -				  port_name(port));
> +				  phy_name(phy));
>  	}
>  	gen11_dsi_gate_clocks(encoder);
>  }
> @@ -1163,25 +1169,25 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> +	enum phy phy;
>  	u32 tmp;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
>  		intel_wakeref_t wakeref;
>  
> -		wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
> +		wakeref = fetch_and_zero(&intel_dsi->io_wakeref[phy]);
>  		intel_display_power_put(dev_priv,
> -					port == PORT_A ?
> +					phy == PHY_A ?
>  					POWER_DOMAIN_PORT_DDI_A_IO :
>  					POWER_DOMAIN_PORT_DDI_B_IO,
>  					wakeref);
>  	}
>  
>  	/* set mode to DDI */
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		tmp = I915_READ(ICL_DSI_IO_MODECTL(phy));
>  		tmp &= ~COMBO_PHY_MODE_DSI;
> -		I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
> +		I915_WRITE(ICL_DSI_IO_MODECTL(phy), tmp);
>  	}
>  }
>  
> @@ -1278,7 +1284,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>  	adjusted_mode->flags = 0;
>  
>  	/* Dual link goes to trancoder DSI'0' */
> -	if (intel_dsi->ports == BIT(PORT_B))
> +	if (intel_dsi->phys == BIT(PHY_B))
>  		pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
>  	else
>  		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
> @@ -1303,7 +1309,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum transcoder dsi_trans;
>  	intel_wakeref_t wakeref;
> -	enum port port;
> +	enum phy phy;
>  	bool ret = false;
>  	u32 tmp;
>  
> @@ -1312,8 +1318,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
>  	if (!wakeref)
>  		return false;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		dsi_trans = dsi_port_to_transcoder(port);
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
> +		dsi_trans = dsi_phy_to_transcoder(phy);
>  		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
>  		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
>  		case TRANS_DDI_EDP_INPUT_A_ON:
> @@ -1552,6 +1558,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>  	struct drm_connector *connector;
>  	struct drm_display_mode *fixed_mode;
>  	enum port port;
> +	enum phy phy;
>  
>  	if (!intel_bios_is_dsi_present(dev_priv, &port))
>  		return;
> @@ -1613,21 +1620,22 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>  	intel_panel_setup_backlight(connector, INVALID_PIPE);
>  
>  	if (dev_priv->vbt.dsi.config->dual_link)
> -		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
> +		intel_dsi->phys = BIT(PHY_A) | BIT(PHY_B);
>  	else
> -		intel_dsi->ports = BIT(port);
> +		intel_dsi->phys = BIT(port);  /* since port==phy */
>  
>  	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
>  	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> +	for_each_dsi_phy(phy, intel_dsi->phys) {
>  		struct intel_dsi_host *host;
>  
> -		host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
> +		host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops,
> +					   (enum port)phy);
>  		if (!host)
>  			goto err;
>  
> -		intel_dsi->dsi_hosts[port] = host;
> +		intel_dsi->dsi_hosts[phy] = host;
>  	}
>  
>  	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
> index b15be5814599..5d0610fb85a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -125,7 +125,10 @@ struct intel_dsi {
>  struct intel_dsi_host {
>  	struct mipi_dsi_host base;
>  	struct intel_dsi *intel_dsi;
> -	enum port port;
> +	union {
> +		enum port port;		/* VLV DSI */
> +		enum phy phy;		/* ICL DSI */
> +	};
>  
>  	/* our little hack */
>  	struct mipi_dsi_device *device;

-- 
Jani Nikula, Intel Open Source Graphics Center
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