On Thu, Sep 05, 2019 at 01:37:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The panel fitter imposes extra limits on the maximum pipe source
> size we can use. Check for that.
>
> v2: Skip the checks if the crtc is disabled
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 348071db8b4c..ccec2b54677d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11768,6 +11768,57 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> }
>
> +static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int max_src_w, max_src_h;
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + max_src_w = 5120;
> + max_src_h = 4320;
> + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + max_src_w = crtc->pipe == PIPE_A ? 5120 : 4096;
> + max_src_h = 4096;
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> + max_src_w = 4096;
> + max_src_h = 4096;
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> + /*
> + * PF0 7x5 capable
> + * PF1 3x3 capable (could be switched to 7x5
> + * mode on HSW when PF2 unused)
> + * PF2 3x3 capable
> + *
> + * This assumes we use a 1:1 mapping between pipe and PF.
> + */
> + max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
> + max_src_h = 4096;
> + } else {
> + max_src_w = 4096;
> + max_src_h = 4096;
> + }
> +
> + if (crtc_state->pipe_src_w > max_src_w ||
> + crtc_state->pipe_src_h > max_src_h) {
> + DRM_DEBUG_KMS("pipe %c source size (%dx%d) exceeds pfit max (%dx%d)\n",
> + pipe_name(crtc->pipe), crtc_state->pipe_src_w,
> + crtc_state->pipe_src_h, max_src_w, max_src_h);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->base.enable ||
We might actually consider clearing most of the crtc state for disabled
pipes. Would avoid having to sprinkle these checks all over the place.
But I haven't really thought through the implications of doing that.
> + !crtc_state->pch_pfit.enabled)
> + return 0;
> +
> + return intel_pch_pfit_check_src_size(crtc_state);
> +}
> +
> static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> struct drm_crtc_state *crtc_state)
> {
> @@ -11791,6 +11842,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> return ret;
> }
>
> + if (!HAS_GMCH(dev_priv)) {
> + ret = intel_pch_pfit_check(pipe_config);
> + if (ret)
> + return ret;
> + }
> +
> /*
> * May need to update pipe gamma enable bits
> * when C8 planes are getting enabled/disabled.
> --
> 2.21.0
--
Ville Syrjälä
Intel
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