On Mon, 2019-09-02 at 21:08 +0300, Jani Nikula wrote:
> Replace device info number of pipes with a bit mask of available
> pipes. This will prove handy in the future. There's still a bunch of
> future work to do to actually allow a non-consecutive mask of pipes,
> but
> it's a start. No functional changes.
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 24 ++++++++++++--------
> ----
> drivers/gpu/drm/i915/intel_device_info.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index f4fc72e2118c..6557cd8ddd7a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2182,9 +2182,9 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> #define GT_FREQUENCY_MULTIPLIER 50
> #define GEN9_FREQ_SCALER 3
>
> -#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
> +#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)-
> >pipe_mask))
>
> -#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
> +#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
>
> static inline bool intel_vtd_active(void)
> {
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index fbe98a2db88e..17ddc03df005 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -147,7 +147,7 @@
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_overlay = 1, \
> .display.cursor_needs_physical = 1, \
> .display.overlay_needs_physical = 1, \
> @@ -165,7 +165,7 @@
>
> #define I845_FEATURES \
> GEN(2), \
> - .num_pipes = 1, \
> + .pipe_mask = BIT(PIPE_A), \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> .display.has_gmch = 1, \
> @@ -203,7 +203,7 @@ static const struct intel_device_info
> intel_i865g_info = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .engine_mask = BIT(RCS0), \
> @@ -287,7 +287,7 @@ static const struct intel_device_info
> intel_pineview_m_info = {
>
> #define GEN4_FEATURES \
> GEN(4), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> @@ -337,7 +337,7 @@ static const struct intel_device_info
> intel_gm45_info = {
>
> #define GEN5_FEATURES \
> GEN(5), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> @@ -363,7 +363,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
>
> #define GEN6_FEATURES \
> GEN(6), \
> - .num_pipes = 2, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -411,7 +411,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> - .num_pipes = 3, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -462,7 +462,7 @@ static const struct intel_device_info
> intel_ivybridge_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> .gt = 2,
> - .num_pipes = 0, /* legal, last one wins */
> + .pipe_mask = 0, /* legal, last one wins */
> .has_l3_dpf = 1,
> };
>
> @@ -470,7 +470,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .num_pipes = 2,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_rps = true,
> @@ -560,7 +560,7 @@ static const struct intel_device_info
> intel_broadwell_gt3_info = {
> static const struct intel_device_info intel_cherryview_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .num_pipes = 3,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .display.has_hotplug = 1,
> .is_lp = 1,
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@ -631,7 +631,7 @@ static const struct intel_device_info
> intel_skylake_gt4_info = {
> .is_lp = 1, \
> .display.has_hotplug = 1, \
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> \
> - .num_pipes = 3, \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .has_64bit_reloc = 1, \
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> @@ -792,7 +792,7 @@ static const struct intel_device_info
> intel_elkhartlake_info = {
> static const struct intel_device_info intel_tigerlake_12_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_TIGERLAKE),
> - .num_pipes = 4,
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) |
> BIT(PIPE_D),
> .require_force_probe = 1,
> .display.has_modular_fia = 1,
> .engine_mask =
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index d9b5baaef5d0..50b05a5de53b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -896,7 +896,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (i915_modparams.disable_display) {
> DRM_INFO("Display disabled (module parameter)\n");
> - info->num_pipes = 0;
> + info->pipe_mask = 0;
> } else if (HAS_DISPLAY(dev_priv) &&
> (IS_GEN_RANGE(dev_priv, 7, 8)) &&
> HAS_PCH_SPLIT(dev_priv)) {
> @@ -917,14 +917,14 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> (HAS_PCH_CPT(dev_priv) &&
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> - info->num_pipes = 0;
> + info->pipe_mask = 0;
> } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> DRM_INFO("PipeC fused off\n");
> - info->num_pipes -= 1;
> + info->pipe_mask &= ~BIT(PIPE_C);
> }
> } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
> u32 dfsm = I915_READ(SKL_DFSM);
> - u8 enabled_mask = BIT(info->num_pipes) - 1;
> + u8 enabled_mask = info->pipe_mask;
>
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> enabled_mask &= ~BIT(PIPE_A);
> @@ -945,7 +945,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> DRM_ERROR("invalid pipe fuse configuration:
> enabled_mask=0x%x\n",
> enabled_mask);
> else
> - info->num_pipes = hweight8(enabled_mask);
> + info->pipe_mask = enabled_mask;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 92e0c2e0954c..d4c288860aed 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -161,7 +161,7 @@ struct intel_device_info {
>
> u32 display_mmio_offset;
>
> - u8 num_pipes;
> + u8 pipe_mask;
>
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
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