On Wed, Sep 04, 2019 at 02:34:16PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
>
> DP_TP_{CTL,STATUS} should only be programmed when the encoder is intel_dp.
> Checking its current usages intel_disable_ddi_buf() is the only
> offender, with other places being protected by checks like
> pipe_config->fec_enable that is only set by intel_dp.
>
> v3 (José):
> - Using intel_crtc_has_dp_encoder() instead of intel_encoder_is_dp()
> (Ville)
>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1fe0bf01e580..ec132cd6add8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3465,10 +3465,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> wait = true;
> }
>
> - val = I915_READ(DP_TP_CTL(port));
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(DP_TP_CTL(port), val);
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + val = I915_READ(DP_TP_CTL(port));
> + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(DP_TP_CTL(port), val);
> + }
>
> /* Disable FEC in DP Sink */
> intel_ddi_disable_fec_state(encoder, crtc_state);
> --
> 2.23.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
