On Tue, 2019-09-03 at 10:16 -0700, Matt Roper wrote:
> On Thu, Aug 29, 2019 at 01:37:55PM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 29, 2019 at 02:25:50AM -0700, Lucas De Marchi wrote:
> > > DP_TP_{CTL,STATUS} should only be programmed when the encoder is
> > > intel_dp.
> > > Checking its current usages intel_disable_ddi_buf() is the only
> > > offender, with other places being protected by checks like
> > > pipe_config->fec_enable that is only set by intel_dp.
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++----
> > > 1 file changed, 6 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 3180dacb5be4..df3e4fe7e3e9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -3462,10 +3462,12 @@ static void intel_disable_ddi_buf(struct
> > > intel_encoder *encoder,
> > > wait = true;
> > > }
> > >
> > > - val = I915_READ(DP_TP_CTL(port));
> > > - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> > > - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > > - I915_WRITE(DP_TP_CTL(port), val);
> > > + if (intel_encoder_is_dp(encoder)) {
> >
> > Doesn't really make sense to me. Either we just do it (because a
> > DDI is
> > just a DDI so DP_TP_CTL does exist always), or we only do it when
> > driving
> > DP and not when driving HDMI.
>
> I agree; I don't think there's a need to avoid program programming
> the
> register just because we weren't previously in DP mode.
The problem of always programing DP_TP_CTL comes with TGL, when
DP_TP_CTL() moves to transcoder, see next patch: drm/i915/tgl: move
DP_TP_* to transcoder.
We are adding intel_dp->regs.dp_tp_ctl and initializing(this is
necessary for MST for SST we could keep the current approach) it in DP
paths, we could move it to intel_encoder or intel_digital_port and
initialized it for HDMI too but it would not make any sense for someone
reading HDMI sequences.
And to move this to a DP specific function would force us to create
another function to execute the last "wait DDI_BUF_CTL to idle".
BSpec: 53339 and 22243
Personally I prefer this patch solution but let me know your thoughts
after this explanation.
>
> But I do question whether a RMW is necessary; it seems like just
> writing
> a constant 0 to this register would be sufficient for the disable
> sequence.
>
>
> Matt
>
> > For the latter I would perhaps suggest moving all this extra junk
> > out
> > from intel_disable_ddi_buf() into the DP specific code paths,
> > leaving
> > just the actual DDI_BUF_CTL disable here.
> >
> > > + val = I915_READ(DP_TP_CTL(port));
> > > + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> > > + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > > + I915_WRITE(DP_TP_CTL(port), val);
> > > + }
> > >
> > > /* Disable FEC in DP Sink */
> > > intel_ddi_disable_fec_state(encoder, crtc_state);
> > > --
> > > 2.23.0
> >
> > --
> > Ville Syrjälä
> > Intel
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