As part of the DPLL enabling sequence we're supposed to wait for the DPLL lock to be reflected in the DPLL_STATUS register after programming the appropriate control registers. The bspec doesn't tell us how long we should wait for this to happen, so we're currently reusing the 5ms timeout that the bspec suggested on BDW. We're hitting occasional timeouts while waiting for DPLL1 to lock on the CFL system we have in CI, so let's bump the timeout to 10ms and see if that eliminates these failures. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107345 Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b8148f838354..089b36dcf470 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -1000,7 +1000,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, I915_WRITE(regs[id].ctl, I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); - if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) + if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 10)) DRM_ERROR("DPLL %d not locked\n", id); } -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
