Regards
Shashank
On 8/27/2019 10:57 AM, Ramalingam C wrote:
On 2019-08-27 at 10:49:25 +0530, Sharma, Shashank wrote:
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx>
---
.../drm/i915/display/intel_display_types.h | 7 +++
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
5 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 449abaea619f..fc85b3e284d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -388,6 +388,13 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ /*
+ * HDCP register access for gen12+ need the transcoder associated.
+ * Transcoder attached to the connector could be changed at modeset.
+ * Hence caching the transcoder here.
+ */
+ enum transcoder cpu_transcoder;
attached_transcoder to be inline with MEI counterpart of the code ?
This is needed so that we can use this to get the offset of register.
Need not be inline with MEI.
:) I meant in the MEI side we are using name "attached_transcoder" so
using the same in I915 also would be easy to understand. But this is not
important, I will leave it to you.
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 921ad0a2f7ba..ba5317d56da7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2244,6 +2244,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
+ intel_hdcp_transcoder_config(intel_connector,
+ pipe_config->cpu_transcoder);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 534832f435dc..1e5548833e8f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1762,13 +1762,60 @@ enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port)
}
}
+static inline
+enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
+{
+ switch (cpu_transcoder) {
+ case TRANSCODER_A ... TRANSCODER_D:
+ return (enum mei_fw_tc)(cpu_transcoder | 0x10);
Again, as this is in context of HDCP, we should not entertain transcoders
below. Or we should move this function in a more generic file like
intel_display.c or intel_ddi.c
This is specific to hdcp. So let it be here. We will fill invalid
TRANSCODER for all non HDCO capable transcoders. Hope that works for
you.
Sure.
+ case TRANSCODER_EDP:
+ return MEI_TC_EDP;
+ case TRANSCODER_DSI_0:
+ return MEI_TC_DSI0;
+ case TRANSCODER_DSI_1:
+ return MEI_TC_DSI1;
+ default:
+ return MEI_INVALID_TRANSCODER;
+ }
+}
+
+void intel_hdcp_transcoder_config(struct intel_connector *connector,
+ enum transcoder cpu_transcoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+
+ if (!hdcp->shim)
+ return;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
Ah, so this is the gen_check which I was talking about in previous patch :-)
+ mutex_lock(&hdcp->mutex);
+ hdcp->cpu_transcoder = cpu_transcoder;
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ mutex_unlock(&hdcp->mutex);
+ }
+}
+
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ struct intel_crtc *crtc;
+
+ if (INTEL_GEN(dev_priv) < 12) {
+ data->fw_ddi =
+ intel_get_mei_fw_ddi_index(connector->encoder->port);
+ } else {
+ crtc = to_intel_crtc(connector->base.state->crtc);
+ if (crtc) {
+ hdcp->cpu_transcoder = crtc->config->cpu_transcoder;
+ data->fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ }
+ data->fw_ddi = intel_get_mei_fw_ddi_index(PORT_NONE);
I dint understand this, why PORT_NONE ?
ME FW API expects invalid PORT for GEN12+. Hence we assign the required
value here. May be I will add that info as doc here.
-Ram
Yes, please add a comment.
- Shashank
- Shashank
+ }
- data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port);
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 59a2b40405cc..41c1053d9e38 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -16,10 +16,13 @@ struct drm_i915_private;
struct intel_connector;
struct intel_hdcp_shim;
enum port;
+enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
+void intel_hdcp_transcoder_config(struct intel_connector *connector,
+ enum transcoder cpu_transcoder);
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e02f0faecf02..6e9bb6bd1ee2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2431,6 +2431,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
return -EINVAL;
}
+ intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
+ pipe_config->cpu_transcoder);
+
return 0;
}
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
