Quoting Stuart Summers (2019-08-21 00:05:44) > Currently, the subslice_mask runtime parameter is stored as an > array of subslices per slice. Expand the subslice mask array to > better match what is presented to userspace through the > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is > then calculated: > slice * subslice stride + subslice index / 8 > > v2: Fix 32-bit build > v3: Use new helper function in SSEU workaround warning message > > Signed-off-by: Stuart Summers <stuart.summers@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_sseu.c | 27 ++++++++++++++++++++- > drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++-- > drivers/gpu/drm/i915/i915_debugfs.c | 5 +++- > drivers/gpu/drm/i915/intel_device_info.c | 8 +++--- > 5 files changed, 40 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index 5d537ec97fcc..eae1c7b20688 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > return total; > } > > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) > +{ > + int i, offset = slice * sseu->ss_stride; > + u32 mask = 0; > + > + if (slice >= sseu->max_slices) { > + DRM_ERROR("%s: invalid slice %d, max: %d\n", > + __func__, slice, sseu->max_slices); > + return 0; > + } That's a programmer error, we only need it during development. I am a proponent of making it explode as early as possible and make people fix it rather than ignore it. > + if (sseu->ss_stride > sizeof(mask)) { > + DRM_ERROR("%s: invalid subslice stride %d, max: %u\n", > + __func__, sseu->ss_stride, > + (unsigned int)sizeof(mask)); > + return 0; > + } Put the assertion in the constructor (set_sseu_info or whatever it was called) > + > + for (i = 0; i < sseu->ss_stride; i++) > + mask |= (u32)sseu->subslice_mask[offset + i] << > + i * BITS_PER_BYTE; Otherwise, the actual conversions look fairly straightforward, Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx