On Thu, Aug 15, 2019 at 02:58:59PM -0700, Matt Roper wrote:
> From the bspec:
>
> "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> programmed value doesn’t match the render target surface address
> programmed. This would disable render engine from generating
> modify messages to FBC unit in display."
This looks a bit peculiar. That magic value seems to imply that the
RT_VALID bit no longer functions as intended. I filed a spec issue to
get some clarification on this.
>
> Bspec: 11388
> Bspec: 33451
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..29b50e2c0627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> /* allow headerless messages for preemptible GPGPU context */
> WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> +
> + /* Wa_1604278689:icl,ehl */
> + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> + 0, /* write-only register; skip validation */
> + 0xFFFFFFFF);
> + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index def6dbdc7e2e..14af1b1dc0d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3214,6 +3214,7 @@ enum i915_power_well_id {
>
> /* Framebuffer compression for Ivybridge */
> #define IVB_FBC_RT_BASE _MMIO(0x7020)
> +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
That register seems to be BDW+ actually.
>
> #define IPS_CTL _MMIO(0x43408)
> #define IPS_ENABLE (1 << 31)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
