On Wed, Aug 14, 2019 at 02:29:57PM +0000, Shankar, Uma wrote: > > > >-----Original Message----- > >From: james qian wang (Arm Technology China) [mailto:james.qian.wang@xxxxxxx] > >Sent: Tuesday, August 13, 2019 3:12 PM > >To: Shankar, Uma <uma.shankar@xxxxxxxxx> > >Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-devel@xxxxxxxxxxxxxxxxxxxxx; Syrjala, Ville > ><ville.syrjala@xxxxxxxxx>; emil.l.velikov@xxxxxxxxx; Lankhorst, Maarten > ><maarten.lankhorst@xxxxxxxxx>; nd <nd@xxxxxxx> > >Subject: Re: [v7,01/16] drm: Add Enhanced Gamma LUT precision structure > > > >On Fri, Mar 29, 2019 at 01:45:59AM +0530, Uma Shankar wrote: > >> Existing LUT precision structure is having only 16 bit precision. This > >> is not enough for upcoming enhanced hardwares and advance usecases > >> like HDR processing. Hence added a new structure with 32 bit precision > >> values. Also added the code, for extracting the same from values > >> passed from userspace. > >> > >> v4: Rebase > >> > >> v5: Relocated the helper function to drm_color_mgmt.c. Declared the > >> same in a header file (Alexandru Gheorghe) > >> > >> v6: Enhanced gamma lut structure to take U32.32 format as input. > >> This is needed for HDR usecase which require higher precision. > >> > >> v7: Addressed Maarten's review comments and fixed the calculation. > >> > >> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx> > >> Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@xxxxxxx> > > > >Hi Uma > > > >When can we merge these plane color-mgmt support into upstream ? > >or can we merge the DRM-CORE part patches firstly? > > Hi James, > I will refresh this series by early next week. We will try to prioritize this development and speed > up with merge. > Regards, > Uma Shankar hi Uma: thank you very much Best Regards, James > >thanks > >james > > > >> --- > >> drivers/gpu/drm/drm_color_mgmt.c | 20 ++++++++++++++++++++ > >> include/drm/drm_color_mgmt.h | 1 + > >> include/uapi/drm/drm_mode.h | 15 +++++++++++++++ > >> 3 files changed, 36 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/drm_color_mgmt.c > >> b/drivers/gpu/drm/drm_color_mgmt.c > >> index d5d34d0..79ff874 100644 > >> --- a/drivers/gpu/drm/drm_color_mgmt.c > >> +++ b/drivers/gpu/drm/drm_color_mgmt.c > >> @@ -128,6 +128,26 @@ uint32_t drm_color_lut_extract(uint32_t > >> user_input, uint32_t bit_precision) } > >> EXPORT_SYMBOL(drm_color_lut_extract); > >> > >> +/* > >> + * Added to accommodate enhanced LUT precision. > >> + * Max LUT precision is 32 bits. > >> + */ > >> +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision) { > >> + u64 val = user_input & 0xffffffff; > >> + u32 max = 0xffffffff >> (32 - bit_precision); > >> + > >> + /* Round only if we're not using full precision. */ > >> + if (bit_precision < 32) { > >> + val += 1UL << (32 - bit_precision - 1); > >> + val >>= 32 - bit_precision; > >> + } > >> + > >> + return ((user_input & 0xffffffff00000000) | > >> + clamp_val(val, 0, max)); > >> +} > >> +EXPORT_SYMBOL(drm_color_lut_extract_ext); > >> + > >> /** > >> * drm_crtc_enable_color_mgmt - enable color management properties > >> * @crtc: DRM CRTC > >> diff --git a/include/drm/drm_color_mgmt.h > >> b/include/drm/drm_color_mgmt.h index d1c662d..c9d2746 100644 > >> --- a/include/drm/drm_color_mgmt.h > >> +++ b/include/drm/drm_color_mgmt.h > >> @@ -30,6 +30,7 @@ > >> struct drm_plane; > >> > >> uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t > >> bit_precision); > >> +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision); > >> > >> void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, > >> uint degamma_lut_size, > >> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h > >> index 09d7296..ca81410 100644 > >> --- a/include/uapi/drm/drm_mode.h > >> +++ b/include/uapi/drm/drm_mode.h > >> @@ -629,6 +629,21 @@ struct drm_color_lut { > >> __u16 reserved; > >> }; > >> > >> +/* > >> + * Creating 64 bit palette entries for better data > >> + * precision. This will be required for HDR and > >> + * similar color processing usecases. > >> + */ > >> +struct drm_color_lut_ext { > >> + /* > >> + * Data is U32.32 fixed point format. > >> + */ > >> + __u64 red; > >> + __u64 green; > >> + __u64 blue; > >> + __u64 reserved; > >> +}; > >> + > >> #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define > >> DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define > >> DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
