>From my tests this workaround is needed otherwise we read the wrong
number of slices later on. It's sent as a FIXME since I couldn't find
any documentation saying this applies to TGL. Fix the following warning:
[ 82.905527] WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) != default_mcr_s_ss_
select)
[ 82.905618] WARNING: CPU: 3 PID: 1118 at drivers/gpu/drm/i915/intel_engine_cs
.c:927 intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905629] Modules linked in: i915
[ 82.905642] CPU: 3 PID: 1118 Comm: cat Tainted: G U W 4.17.0-rc7
-demarchi+ #7
[ 82.905653] Hardware name: Bochs Bochs, BIOS Bochs 01/01/2007
[ 82.905711] RIP: 0010:intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905722] RSP: 0018:ffffb5a381317be8 EFLAGS: 00010092
[ 82.905734] RAX: 0000000000000048 RBX: 0000000008000000 RCX: ffffffff9165c748
[ 82.905745] RDX: 0000000000000001 RSI: 0000000000000086 RDI: 0000000000000087
[ 82.905756] RBP: 0000000000000001 R08: 297463656c65735f R09: 00000000000003c2
[ 82.905768] R10: 5f746c7561666564 R11: 73735f735f72636d R12: 0000000000000000
[ 82.905779] R13: 0000000000000000 R14: ffff98b598a00000 R15: 0000000000000000
[ 82.905791] FS: 00007f6e6fa5e500(0000) GS:ffff98b5bfb80000(0000) knlGS:00000
00000000000
[ 82.905802] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 82.905813] CR2: 00007f6e6fa3b000 CR3: 0000000232606000 CR4: 00000000000006e0
[ 82.905824] Call Trace:
[ 82.905883] i915_hangcheck_info+0xf7/0x3d0 [i915]
[ 82.905898] seq_read+0x15b/0x440
[ 82.905911] ? __handle_mm_fault+0xaf9/0x1270
[ 82.905923] full_proxy_read+0x53/0x80
[ 82.905936] __vfs_read+0x26/0x140
[ 82.905949] vfs_read+0x8a/0x140
[ 82.905961] ksys_read+0x3f/0xa0
[ 82.905974] do_syscall_64+0x5b/0x160
[ 82.905986] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 82.905998] RIP: 0033:0x7f6e6f585701
[ 82.906009] RSP: 002b:00007ffff94652e8 EFLAGS: 00000246 ORIG_RAX: 00000000000
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b58e1e6e610f..a227a0272f3c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -768,7 +768,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* by default, to make sure we correctly read certain registers
* later on (in the range 0xB100 - 0xB3FF).
*
- * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl,tgl
* Before any MMIO read into slice/subslice specific registers, MCR
* packet control register needs to be programmed to point to any
* enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -900,6 +900,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
+ wa_init_mcr(i915, wal);
}
static void
--
2.21.0
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