On Sat, Aug 10, 2019 at 12:02:18AM +0530, Anshuman Gupta wrote: > As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled > and DC3CO should be enabled only during VIDEO playback. > Which essentially means both can DC5 and DC3CO can not be > enabled at same time, it makes DC3CO and DC5 mutual exclusive. > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: Animesh Manna <animesh.manna@xxxxxxxxx> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > Signed-off-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index c9e92d48cdab..167839060154 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > > + /* DC3CO and DC5/6 are mutually exclusive */ > + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) > + tgl_allow_dc3co(dev_priv); Ah ok, here is the re-enabling I was looking for in the previous patch. I think this change could've been part of the previous patch. However this re-enables DC3CO regardless of any PSR2 condition. > + > dev_priv->display.get_cdclk(dev_priv, &cdclk_state); > /* Can't read out voltage_level so can't use intel_cdclk_changed() */ > WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); > @@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, > if (!dev_priv->csr.dmc_payload) > return; > > + /* DC3CO and DC5/6 are mutually exclusive */ > + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) > + tgl_disallow_dc3co(dev_priv); > + > if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) > skl_enable_dc6(dev_priv); > else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) > -- > 2.21.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
