Quoting Mika Kuoppala (2019-08-09 15:56:53) > Our current avoidance of non readable mcr range was not > inclusive enough. Extend the start and end. > > References: HSDES#1405586840 > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 704ace01e7f5..eb03cd507b28 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1434,7 +1434,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset) > * which only controls CPU initiated MMIO. Routing does not > * work for CS access so we cannot verify them on this path. > */ > - if (INTEL_GEN(i915) >= 8 && (offset >= 0xb100 && offset <= 0xb3ff)) > + if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff)) > return true; Ok, I haven't found where this range is spelled out, but I have found examples outside the previous range; and b000 gets referred to as the base. Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
