>-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 30, 2019 1:07 PM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx; Shankar, Uma ><uma.shankar@xxxxxxxxx>; Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx> >Subject: [v2 0/6] Support mipi dsi video mode on TGL > >Most of the sequence remains as same as that of ICL. >This series includes the changes needed for TGL. Series pushed to dinq. Thanks for the patches. Regards, Uma Shankar >Vandita Kulkarni (6): > drm/i915/tgl/dsi: Program TRANS_VBLANK register > drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl > drm/i915/tgl/dsi: Do not override TA_SURE > drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping > drm/i915/tgl: Add mipi dsi support for TGL > drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode > > drivers/gpu/drm/i915/display/icl_dsi.c | 54 ++++++++++++++------ > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > 3 files changed, 40 insertions(+), 16 deletions(-) > >-- >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
