On Wed, Aug 07, 2019 at 05:49:39PM +0300, Jani Nikula wrote:
> Valleyview is the only platform that requires the Gunit s0ix save
> state. Allocate it dynamically instead of burdening all platforms with
> it in drm_i915_private.
>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Looks ok to me,
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 79 ++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 64 +-------------------------
> 2 files changed, 79 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index efe904626bf5..c1483cd8e76c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2559,11 +2559,81 @@ static int i915_pm_restore(struct device *kdev)
> * a black-box for the driver. Further investigation is needed to reduce the
> * saved/restored registers even further, by following the same 3 criteria.
> */
> +
> +struct vlv_s0ix_state {
> + /* GAM */
> + u32 wr_watermark;
> + u32 gfx_prio_ctrl;
> + u32 arb_mode;
> + u32 gfx_pend_tlb0;
> + u32 gfx_pend_tlb1;
> + u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> + u32 media_max_req_count;
> + u32 gfx_max_req_count;
> + u32 render_hwsp;
> + u32 ecochk;
> + u32 bsd_hwsp;
> + u32 blt_hwsp;
> + u32 tlb_rd_addr;
> +
> + /* MBC */
> + u32 g3dctl;
> + u32 gsckgctl;
> + u32 mbctl;
> +
> + /* GCP */
> + u32 ucgctl1;
> + u32 ucgctl3;
> + u32 rcgctl1;
> + u32 rcgctl2;
> + u32 rstctl;
> + u32 misccpctl;
> +
> + /* GPM */
> + u32 gfxpause;
> + u32 rpdeuhwtc;
> + u32 rpdeuc;
> + u32 ecobus;
> + u32 pwrdwnupctl;
> + u32 rp_down_timeout;
> + u32 rp_deucsw;
> + u32 rcubmabdtmr;
> + u32 rcedata;
> + u32 spare2gh;
> +
> + /* Display 1 CZ domain */
> + u32 gt_imr;
> + u32 gt_ier;
> + u32 pm_imr;
> + u32 pm_ier;
> + u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> +
> + /* GT SA CZ domain */
> + u32 tilectl;
> + u32 gt_fifoctl;
> + u32 gtlc_wake_ctrl;
> + u32 gtlc_survive;
> + u32 pmwgicz;
> +
> + /* Display 2 CZ domain */
> + u32 gu_ctl0;
> + u32 gu_ctl1;
> + u32 pcbr;
> + u32 clock_gate_dis2;
> +};
> +
> static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
> int i;
>
> + if (!s) {
> + s = devm_kmalloc(dev_priv->drm.dev, sizeof(*s), GFP_KERNEL);
> + if (!s)
> + return;
> + dev_priv->vlv_s0ix_state = s;
> + }
> +
> /* GAM 0x4000-0x4770 */
> s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
> s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
> @@ -2642,10 +2712,15 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>
> static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
> u32 val;
> int i;
>
> + if (!s) {
> + DRM_DEBUG_KMS("gunit restore without save state\n");
> + return;
> + }
> +
> /* GAM 0x4000-0x4770 */
> I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
> I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7d424ddd3523..30e33103b845 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -580,67 +580,7 @@ struct i915_suspend_saved_registers {
> u16 saveGCDGMBUS;
> };
>
> -struct vlv_s0ix_state {
> - /* GAM */
> - u32 wr_watermark;
> - u32 gfx_prio_ctrl;
> - u32 arb_mode;
> - u32 gfx_pend_tlb0;
> - u32 gfx_pend_tlb1;
> - u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> - u32 media_max_req_count;
> - u32 gfx_max_req_count;
> - u32 render_hwsp;
> - u32 ecochk;
> - u32 bsd_hwsp;
> - u32 blt_hwsp;
> - u32 tlb_rd_addr;
> -
> - /* MBC */
> - u32 g3dctl;
> - u32 gsckgctl;
> - u32 mbctl;
> -
> - /* GCP */
> - u32 ucgctl1;
> - u32 ucgctl3;
> - u32 rcgctl1;
> - u32 rcgctl2;
> - u32 rstctl;
> - u32 misccpctl;
> -
> - /* GPM */
> - u32 gfxpause;
> - u32 rpdeuhwtc;
> - u32 rpdeuc;
> - u32 ecobus;
> - u32 pwrdwnupctl;
> - u32 rp_down_timeout;
> - u32 rp_deucsw;
> - u32 rcubmabdtmr;
> - u32 rcedata;
> - u32 spare2gh;
> -
> - /* Display 1 CZ domain */
> - u32 gt_imr;
> - u32 gt_ier;
> - u32 pm_imr;
> - u32 pm_ier;
> - u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> -
> - /* GT SA CZ domain */
> - u32 tilectl;
> - u32 gt_fifoctl;
> - u32 gtlc_wake_ctrl;
> - u32 gtlc_survive;
> - u32 pmwgicz;
> -
> - /* Display 2 CZ domain */
> - u32 gu_ctl0;
> - u32 gu_ctl1;
> - u32 pcbr;
> - u32 clock_gate_dis2;
> -};
> +struct vlv_s0ix_state;
>
> struct intel_rps_ei {
> ktime_t ktime;
> @@ -1601,7 +1541,7 @@ struct drm_i915_private {
> u32 suspend_count;
> bool power_domains_suspended;
> struct i915_suspend_saved_registers regfile;
> - struct vlv_s0ix_state vlv_s0ix_state;
> + struct vlv_s0ix_state *vlv_s0ix_state;
>
> enum {
> I915_SAGV_UNKNOWN = 0,
> --
> 2.20.1
>
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