Re: [PATCH] drm/i915: split out intel_pch.[ch] from i915_drv.[ch]

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On Wed, Aug 07, 2019 at 03:04:15PM +0300, Jani Nikula wrote:
> Abstract the rather self-contained piece of code from i915_drv.[ch]. No
> functional changes.
> 
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>

Acked-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>

> ---
>  drivers/gpu/drm/i915/Makefile    |   1 +
>  drivers/gpu/drm/i915/i915_drv.c  | 194 -----------------------------
>  drivers/gpu/drm/i915/i915_drv.h  |  60 +--------
>  drivers/gpu/drm/i915/intel_pch.c | 201 +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pch.h |  73 +++++++++++
>  5 files changed, 276 insertions(+), 253 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_pch.c
>  create mode 100644 drivers/gpu/drm/i915/intel_pch.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8fe157f71617..7f710415a525 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -48,6 +48,7 @@ i915-y += i915_drv.o \
>  	  i915_sysfs.o \
>  	  intel_csr.o \
>  	  intel_device_info.o \
> +	  intel_pch.o \
>  	  intel_pm.o \
>  	  intel_runtime_pm.o \
>  	  intel_sideband.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 535209ee4741..5807c1a0dab1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,200 +150,6 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level,
>  	}
>  }
>  
> -/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
> -static enum intel_pch
> -intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
> -{
> -	switch (id) {
> -	case INTEL_PCH_IBX_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> -		WARN_ON(!IS_GEN(dev_priv, 5));
> -		return PCH_IBX;
> -	case INTEL_PCH_CPT_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> -		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
> -		return PCH_CPT;
> -	case INTEL_PCH_PPT_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> -		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
> -		/* PantherPoint is CPT compatible */
> -		return PCH_CPT;
> -	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> -		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> -		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
> -		return PCH_LPT;
> -	case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> -		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> -		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
> -		return PCH_LPT;
> -	case INTEL_PCH_WPT_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> -		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> -		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
> -		/* WildcatPoint is LPT compatible */
> -		return PCH_LPT;
> -	case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> -		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> -		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
> -		/* WildcatPoint is LPT compatible */
> -		return PCH_LPT;
> -	case INTEL_PCH_SPT_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> -		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
> -		return PCH_SPT;
> -	case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> -		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
> -		return PCH_SPT;
> -	case INTEL_PCH_KBP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
> -		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
> -			!IS_COFFEELAKE(dev_priv));
> -		/* KBP is SPT compatible */
> -		return PCH_SPT;
> -	case INTEL_PCH_CNP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
> -		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> -		return PCH_CNP;
> -	case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
> -		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> -		return PCH_CNP;
> -	case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> -		WARN_ON(!IS_COFFEELAKE(dev_priv));
> -		/* CometPoint is CNP Compatible */
> -		return PCH_CNP;
> -	case INTEL_PCH_ICP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Ice Lake PCH\n");
> -		WARN_ON(!IS_ICELAKE(dev_priv));
> -		return PCH_ICP;
> -	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
> -	case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
> -		WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> -		return PCH_MCC;
> -	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> -		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
> -		WARN_ON(!IS_TIGERLAKE(dev_priv));
> -		return PCH_TGP;
> -	default:
> -		return PCH_NONE;
> -	}
> -}
> -
> -static bool intel_is_virt_pch(unsigned short id,
> -			      unsigned short svendor, unsigned short sdevice)
> -{
> -	return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
> -		id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
> -		(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
> -		 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> -		 sdevice == PCI_SUBDEVICE_ID_QEMU));
> -}
> -
> -static unsigned short
> -intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
> -{
> -	unsigned short id = 0;
> -
> -	/*
> -	 * In a virtualized passthrough environment we can be in a
> -	 * setup where the ISA bridge is not able to be passed through.
> -	 * In this case, a south bridge can be emulated and we have to
> -	 * make an educated guess as to which PCH is really there.
> -	 */
> -
> -	if (IS_TIGERLAKE(dev_priv))
> -		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> -	else if (IS_ELKHARTLAKE(dev_priv))
> -		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> -	else if (IS_ICELAKE(dev_priv))
> -		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> -	else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> -		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> -	else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
> -		id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
> -	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> -		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
> -	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> -		id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
> -	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> -		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
> -	else if (IS_GEN(dev_priv, 5))
> -		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
> -
> -	if (id)
> -		DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
> -	else
> -		DRM_DEBUG_KMS("Assuming no PCH\n");
> -
> -	return id;
> -}
> -
> -static void intel_detect_pch(struct drm_i915_private *dev_priv)
> -{
> -	struct pci_dev *pch = NULL;
> -
> -	/*
> -	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
> -	 * make graphics device passthrough work easy for VMM, that only
> -	 * need to expose ISA bridge to let driver know the real hardware
> -	 * underneath. This is a requirement from virtualization team.
> -	 *
> -	 * In some virtualized environments (e.g. XEN), there is irrelevant
> -	 * ISA bridge in the system. To work reliably, we should scan trhough
> -	 * all the ISA bridge devices and check for the first match, instead
> -	 * of only checking the first one.
> -	 */
> -	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> -		unsigned short id;
> -		enum intel_pch pch_type;
> -
> -		if (pch->vendor != PCI_VENDOR_ID_INTEL)
> -			continue;
> -
> -		id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> -
> -		pch_type = intel_pch_type(dev_priv, id);
> -		if (pch_type != PCH_NONE) {
> -			dev_priv->pch_type = pch_type;
> -			dev_priv->pch_id = id;
> -			break;
> -		} else if (intel_is_virt_pch(id, pch->subsystem_vendor,
> -					 pch->subsystem_device)) {
> -			id = intel_virt_detect_pch(dev_priv);
> -			pch_type = intel_pch_type(dev_priv, id);
> -
> -			/* Sanity check virtual PCH id */
> -			if (WARN_ON(id && pch_type == PCH_NONE))
> -				id = 0;
> -
> -			dev_priv->pch_type = pch_type;
> -			dev_priv->pch_id = id;
> -			break;
> -		}
> -	}
> -
> -	/*
> -	 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
> -	 * display.
> -	 */
> -	if (pch && !HAS_DISPLAY(dev_priv)) {
> -		DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
> -		dev_priv->pch_type = PCH_NOP;
> -		dev_priv->pch_id = 0;
> -	}
> -
> -	if (!pch)
> -		DRM_DEBUG_KMS("No PCH found.\n");
> -
> -	pci_dev_put(pch);
> -}
> -
>  static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  			       struct drm_file *file_priv)
>  {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7d424ddd3523..43b0d149d114 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -77,6 +77,7 @@
>  #include "gt/uc/intel_uc.h"
>  
>  #include "intel_device_info.h"
> +#include "intel_pch.h"
>  #include "intel_runtime_pm.h"
>  #include "intel_uncore.h"
>  #include "intel_wakeref.h"
> @@ -528,25 +529,6 @@ struct i915_psr {
>  	u16 su_x_granularity;
>  };
>  
> -/*
> - * Sorted by south display engine compatibility.
> - * If the new PCH comes with a south display engine that is not
> - * inherited from the latest item, please do not add it to the
> - * end. Instead, add it right after its "parent" PCH.
> - */
> -enum intel_pch {
> -	PCH_NOP = -1,	/* PCH without south display */
> -	PCH_NONE = 0,	/* No PCH present */
> -	PCH_IBX,	/* Ibexpeak PCH */
> -	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
> -	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
> -	PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
> -	PCH_CNP,        /* Cannon/Comet Lake PCH */
> -	PCH_ICP,	/* Ice Lake PCH */
> -	PCH_MCC,        /* Mule Creek Canyon PCH */
> -	PCH_TGP,	/* Tiger Lake PCH */
> -};
> -
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
>  #define QUIRK_INVERT_BRIGHTNESS (1<<2)
>  #define QUIRK_BACKLIGHT_PRESENT (1<<3)
> @@ -2291,46 +2273,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
>  
> -#define INTEL_PCH_DEVICE_ID_MASK		0xff80
> -#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> -#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> -#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
> -#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
> -#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
> -#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
> -#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
> -#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
> -#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
> -#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
> -#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
> -#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
> -#define INTEL_PCH_CMP_DEVICE_ID_TYPE		0x0280
> -#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
> -#define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
> -#define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
> -#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
> -#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
> -#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
> -#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
> -
> -#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> -#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> -#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> -#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
> -#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
> -#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
> -#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> -#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev_priv) \
> -	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> -	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev_priv) \
> -	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> -	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> -#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> -#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> -#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> -#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>  
>  #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> new file mode 100644
> index 000000000000..fa864d8f2b73
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2019 Intel Corporation.
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_pch.h"
> +
> +/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
> +static enum intel_pch
> +intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
> +{
> +	switch (id) {
> +	case INTEL_PCH_IBX_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> +		WARN_ON(!IS_GEN(dev_priv, 5));
> +		return PCH_IBX;
> +	case INTEL_PCH_CPT_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> +		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
> +		return PCH_CPT;
> +	case INTEL_PCH_PPT_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> +		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
> +		/* PantherPoint is CPT compatible */
> +		return PCH_CPT;
> +	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> +		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> +		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
> +		return PCH_LPT;
> +	case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> +		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> +		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
> +		return PCH_LPT;
> +	case INTEL_PCH_WPT_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
> +		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> +		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
> +		/* WildcatPoint is LPT compatible */
> +		return PCH_LPT;
> +	case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
> +		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
> +		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
> +		/* WildcatPoint is LPT compatible */
> +		return PCH_LPT;
> +	case INTEL_PCH_SPT_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> +		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
> +		return PCH_SPT;
> +	case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> +		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
> +		return PCH_SPT;
> +	case INTEL_PCH_KBP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
> +		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
> +			!IS_COFFEELAKE(dev_priv));
> +		/* KBP is SPT compatible */
> +		return PCH_SPT;
> +	case INTEL_PCH_CNP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
> +		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> +		return PCH_CNP;
> +	case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
> +		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
> +		return PCH_CNP;
> +	case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> +		WARN_ON(!IS_COFFEELAKE(dev_priv));
> +		/* CometPoint is CNP Compatible */
> +		return PCH_CNP;
> +	case INTEL_PCH_ICP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Ice Lake PCH\n");
> +		WARN_ON(!IS_ICELAKE(dev_priv));
> +		return PCH_ICP;
> +	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
> +	case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
> +		WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> +		return PCH_MCC;
> +	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
> +		WARN_ON(!IS_TIGERLAKE(dev_priv));
> +		return PCH_TGP;
> +	default:
> +		return PCH_NONE;
> +	}
> +}
> +
> +static bool intel_is_virt_pch(unsigned short id,
> +			      unsigned short svendor, unsigned short sdevice)
> +{
> +	return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
> +		id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
> +		(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
> +		 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> +		 sdevice == PCI_SUBDEVICE_ID_QEMU));
> +}
> +
> +static unsigned short
> +intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
> +{
> +	unsigned short id = 0;
> +
> +	/*
> +	 * In a virtualized passthrough environment we can be in a
> +	 * setup where the ISA bridge is not able to be passed through.
> +	 * In this case, a south bridge can be emulated and we have to
> +	 * make an educated guess as to which PCH is really there.
> +	 */
> +
> +	if (IS_TIGERLAKE(dev_priv))
> +		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> +	else if (IS_ELKHARTLAKE(dev_priv))
> +		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> +	else if (IS_ICELAKE(dev_priv))
> +		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> +	else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> +		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
> +	else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
> +		id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
> +	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> +		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
> +	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
> +	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> +		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
> +	else if (IS_GEN(dev_priv, 5))
> +		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
> +
> +	if (id)
> +		DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
> +	else
> +		DRM_DEBUG_KMS("Assuming no PCH\n");
> +
> +	return id;
> +}
> +
> +void intel_detect_pch(struct drm_i915_private *dev_priv)
> +{
> +	struct pci_dev *pch = NULL;
> +
> +	/*
> +	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
> +	 * make graphics device passthrough work easy for VMM, that only
> +	 * need to expose ISA bridge to let driver know the real hardware
> +	 * underneath. This is a requirement from virtualization team.
> +	 *
> +	 * In some virtualized environments (e.g. XEN), there is irrelevant
> +	 * ISA bridge in the system. To work reliably, we should scan trhough
> +	 * all the ISA bridge devices and check for the first match, instead
> +	 * of only checking the first one.
> +	 */
> +	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> +		unsigned short id;
> +		enum intel_pch pch_type;
> +
> +		if (pch->vendor != PCI_VENDOR_ID_INTEL)
> +			continue;
> +
> +		id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
> +
> +		pch_type = intel_pch_type(dev_priv, id);
> +		if (pch_type != PCH_NONE) {
> +			dev_priv->pch_type = pch_type;
> +			dev_priv->pch_id = id;
> +			break;
> +		} else if (intel_is_virt_pch(id, pch->subsystem_vendor,
> +					     pch->subsystem_device)) {
> +			id = intel_virt_detect_pch(dev_priv);
> +			pch_type = intel_pch_type(dev_priv, id);
> +
> +			/* Sanity check virtual PCH id */
> +			if (WARN_ON(id && pch_type == PCH_NONE))
> +				id = 0;
> +
> +			dev_priv->pch_type = pch_type;
> +			dev_priv->pch_id = id;
> +			break;
> +		}
> +	}
> +
> +	/*
> +	 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
> +	 * display.
> +	 */
> +	if (pch && !HAS_DISPLAY(dev_priv)) {
> +		DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
> +		dev_priv->pch_type = PCH_NOP;
> +		dev_priv->pch_id = 0;
> +	}
> +
> +	if (!pch)
> +		DRM_DEBUG_KMS("No PCH found.\n");
> +
> +	pci_dev_put(pch);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
> new file mode 100644
> index 000000000000..e6a2d65f19c6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright 2019 Intel Corporation.
> + */
> +
> +#ifndef __INTEL_PCH__
> +#define __INTEL_PCH__
> +
> +struct drm_i915_private;
> +
> +/*
> + * Sorted by south display engine compatibility.
> + * If the new PCH comes with a south display engine that is not
> + * inherited from the latest item, please do not add it to the
> + * end. Instead, add it right after its "parent" PCH.
> + */
> +enum intel_pch {
> +	PCH_NOP = -1,	/* PCH without south display */
> +	PCH_NONE = 0,	/* No PCH present */
> +	PCH_IBX,	/* Ibexpeak PCH */
> +	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
> +	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
> +	PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
> +	PCH_CNP,        /* Cannon/Comet Lake PCH */
> +	PCH_ICP,	/* Ice Lake PCH */
> +	PCH_MCC,        /* Mule Creek Canyon PCH */
> +	PCH_TGP,	/* Tiger Lake PCH */
> +};
> +
> +#define INTEL_PCH_DEVICE_ID_MASK		0xff80
> +#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> +#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> +#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
> +#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
> +#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
> +#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
> +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
> +#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
> +#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
> +#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
> +#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
> +#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
> +#define INTEL_PCH_CMP_DEVICE_ID_TYPE		0x0280
> +#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
> +#define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
> +#define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
> +#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
> +#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
> +#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
> +#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
> +
> +#define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
> +#define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
> +#define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> +#define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
> +#define HAS_PCH_ICP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
> +#define HAS_PCH_CNP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
> +#define HAS_PCH_SPT(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> +#define HAS_PCH_LPT(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> +#define HAS_PCH_LPT_LP(dev_priv) \
> +	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
> +	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev_priv) \
> +	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
> +	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_CPT(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> +#define HAS_PCH_IBX(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> +#define HAS_PCH_NOP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> +#define HAS_PCH_SPLIT(dev_priv)			(INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
> +
> +void intel_detect_pch(struct drm_i915_private *dev_priv);
> +
> +#endif /* __INTEL_PCH__ */
> -- 
> 2.20.1
> 
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