Quoting Chris Wilson (2019-07-25 09:30:25)
> Quoting Takashi Iwai (2019-07-25 09:26:56)
> > On Thu, 25 Jul 2019 10:16:07 +0200,
> > Takashi Iwai wrote:
> > >
> > > On Thu, 25 Jul 2019 10:03:00 +0200,
> > > Chris Wilson wrote:
> > > >
> > > > Just a heads up that icl is consistently showing
> > > >
> > > > <4> [315.478830] snd_hda_intel 0000:00:1f.3: azx_get_response timeout, switching to polling mode: last cmd=0x202f8100
> > > > <4> [316.482799] snd_hda_intel 0000:00:1f.3: No response from codec, disabling MSI: last cmd=0x202f8100
> > > > <3> [508.412915] snd_hda_codec_hdmi hdaudioC0D2: Unable to sync register 0x2f8100. -11
> > > >
> > > > following commits 2756d9143aa5 ("ALSA: hda - Fix intermittent CORB/RIRB
> > > > stall on Intel chips") and a30f1743e4f5 ("ALSA: line6: sizeof (byte) is
> > > > always 1, use that fact.")
> > >
> > > The verb that stalls (0x202f8100) is a read verb (0xf81, Intel
> > > vendor-specific verb for HDMI), so it shouldn't matter whether with or
> > > without write sync, because it needs to read the response in anyway.
> > >
> > > If that patch broke anything, it means that something else was already
> > > broken. Oh well, that ICL crap...
> > >
> > > Is it about the runtime PM, or S3 or S4? The only case we need to
> > > re-issue this verb is only S4, I suppose, so we may skip that in most
> > > cases.
> >
> > Now checking the code, and I believe the workaround applied there can
> > be skipped for non-Haswell chips. Could you try the patch below in
> > addition?
>
> Due to the way patchwork works, this patch will now be tested instead of
> the revert. So watch this space.
Sadly, no change. Patchwork definitely lists this patch as being the one
tested, but maybe send it separately just in case.
-Chris
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