Quoting Tvrtko Ursulin (2019-07-22 12:41:36) > > On 20/07/2019 15:31, Chris Wilson wrote: > > Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as > > the machine stops responding milliseconds after receipt of the reset > > request [GDRT]. By disabling the cached atomics, the hang do not occur > > and we presume the GPU would reset normally for similar hangs. > > > > Reported-by: Jason Ekstrand <jason@xxxxxxxxxxxxxx> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998 > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Jason Ekstrand <jason@xxxxxxxxxxxxxx> > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> > > --- > > Jason reports that Windows is not clearing L3SQCREG4:22 and does not > > suffer the same GPU hang so it is likely some other w/a that interacts > > badly. Fwiw, these 3 are the only registers I could find that mention > > atomic ops (and appear to be part of the same chain for memory access). > > Bit-toggling itself looks fine to me and matches what I could find in > the docs. (All three bits across three registers should be equal.) > > What I am curious about is what are the other consequences of disabling > L3 atomics? Performance drop somewhere? The test I have where it goes from dead to passing, that's a considerable performance improvement ;) I imagine not being able to use L3 for atomics is pretty dire, whether that has any impact, I have no clue. It is still very likely that we see this because we are doing something wrong elsewhere. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
