On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so only set this register on gen < 12.
>
> v2: Generalize check for gen 12 (suggested by José)
> v3: Rebase after enum phy introduction
>
Reviewed-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 93a148684c53..dd2a50b8ba0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val |
> ICL_LANE_ENABLE_AUX);
> + }
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> @@ -487,8 +489,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val &
> ~ICL_LANE_ENABLE_AUX);
> + }
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
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