>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of >Lucas De Marchi >Sent: Friday, July 12, 2019 6:09 PM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Subject: [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts > >For Tiger Lake the DE Port Interrupt Definition bits changed, so use the new bit >definitions. > >Cc: Jose Souza <jose.souza@xxxxxxxxx> >Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> >--- > drivers/gpu/drm/i915/i915_irq.c | 16 +++++++++++----- >drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 14 insertions(+), 5 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >index 256bd2c072c1..6350e9dee653 100644 >--- a/drivers/gpu/drm/i915/i915_irq.c >+++ b/drivers/gpu/drm/i915/i915_irq.c >@@ -2939,19 +2939,25 @@ static void gen11_hpd_irq_handler(struct >drm_i915_private *dev_priv, u32 iir) > > static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) { >- u32 mask = GEN8_AUX_CHANNEL_A; >+ u32 mask; >+ >+ if (INTEL_GEN(dev_priv) >= 12) >+ /* TODO: Add AUX entries for USBC */ >+ return TGL_DE_PORT_AUX_DDIA | >+ TGL_DE_PORT_AUX_DDIB | >+ TGL_DE_PORT_AUX_DDIC; > >+ mask = GEN8_AUX_CHANNEL_A; > if (INTEL_GEN(dev_priv) >= 9) > mask |= GEN9_AUX_CHANNEL_B | > GEN9_AUX_CHANNEL_C | > GEN9_AUX_CHANNEL_D; > >- if (IS_CNL_WITH_PORT_F(dev_priv)) >+ if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11)) > mask |= CNL_AUX_CHANNEL_F; > >- if (INTEL_GEN(dev_priv) >= 11) >- mask |= ICL_AUX_CHANNEL_E | >- CNL_AUX_CHANNEL_F; >+ if (IS_GEN(dev_priv, 11)) >+ mask |= ICL_AUX_CHANNEL_E; > > return mask; > } >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index ff703baf105f..41c8b40eebd5 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -7428,6 +7428,9 @@ enum { > #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) > #define BXT_DE_PORT_GMBUS (1 << 1) > #define GEN8_AUX_CHANNEL_A (1 << 0) >+#define TGL_DE_PORT_AUX_DDIC (1 << 2) >+#define TGL_DE_PORT_AUX_DDIB (1 << 1) >+#define TGL_DE_PORT_AUX_DDIA (1 << 0) > > #define GEN8_DE_MISC_ISR _MMIO(0x44460) #define GEN8_DE_MISC_IMR >_MMIO(0x44464) >-- >2.21.0 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
