>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 2, 2019 9:49 AM
>To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: ville.syrjala@xxxxxxxxxxxxxxx; Nikula, Jani <jani.nikula@xxxxxxxxx>; Shankar, Uma
><uma.shankar@xxxxxxxxx>; Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>
>Subject: [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE
>
>Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or
>below on TGL.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>b/drivers/gpu/drm/i915/display/icl_dsi.c
>index e3980676bcef..d1c50a4186f0 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct
>intel_encoder *encoder)
> * a value '0' inside TA_PARAM_REGISTERS otherwise
> * leave all fields at HW default values.
> */
>- if (intel_dsi_bitrate(intel_dsi) <= 800000) {
>- for_each_dsi_port(port, intel_dsi->ports) {
>- tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>- tmp &= ~TA_SURE_MASK;
>- tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
>- I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>-
>- /* shadow register inside display core */
>- tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>- tmp &= ~TA_SURE_MASK;
>- tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
>- I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>+ if (IS_GEN(dev_priv, 11)) {
>+ if (intel_dsi_bitrate(intel_dsi) <= 800000) {
>+ for_each_dsi_port(port, intel_dsi->ports) {
>+ tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>+ tmp &= ~TA_SURE_MASK;
>+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
>+ I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>+
>+ /* shadow register inside display core */
>+ tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>+ tmp &= ~TA_SURE_MASK;
>+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
>+ I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>+ }
> }
> }
>
>--
>2.21.0.5.gaeb582a
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