== Series Details == Series: Initial support for Tiger Lake (rev8) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip d6bd962a2eb2 drm/i915: Add 4th pipe and transcoder 95c7ae28d487 drm/i915/tgl: add initial Tiger Lake definitions 17ed1276c7b9 drm/i915/tgl: Introduce Tiger Lake PCH 5ad7f4c463f0 drm/i915/tgl: Add TGL PCH detection in virtualized environment f62cc20361e8 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked cdb44f60e265 drm/i915/tgl: Check if pipe D is fused 9c274b6a4602 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A 5b6e27cc5532 drm/i915/tgl: Add power well support d6b06463f2d2 drm/i915/tgl: Add power well to support 4th pipe c13c89a986b0 drm/i915/tgl: Add new pll ids d8b25c49dada drm/i915/tgl: Add pll manager 22cf397c2e61 drm/i915/tgl: Add additional ports for Tiger Lake 1b6b9adeb31d drm/i915/tgl: Add additional PHYs for Tiger Lake 12b705f92223 drm/i915/tgl: init ddi port A-C for Tiger Lake 2cc14230d65d drm/i915/tgl: apply Display WA #1178 to fix type C dongles 23a6017a675e drm/i915/gen12: MBUS B credit change 3f94caf873a3 drm/i915/tgl: Add gmbus gpio pin to port mapping bf6f326339b3 drm/i915/tgl: port to ddc pin mapping 74c7d63fdab7 drm/i915/tgl: Add vbt value mapping for DDC Bus pin 5f78ee1146f5 drm/i915/tgl: Add DPLL registers a995fa3f5008 drm/i915/tgl: Update DPLL clock reference register _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
