On Wed, Jul 10, 2019 at 12:24:15PM -0700, Manasi Navare wrote:
> On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote:
> > On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> > > On TGL+ we support 8K display resolution, hence bump up the vertical
> > > active limits to 4320 in intel_mode_valid()
> > >
> > > v2:
> > > * Checkpatch warning (Manasi)
> > >
> > > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> > > 1 file changed, 7 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f07081815b80..cfceb27e4b9e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> > > DRM_MODE_FLAG_CLKDIV2))
> > > return MODE_BAD;
> > >
> > > - if (INTEL_GEN(dev_priv) >= 9 ||
> > > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 12) {
> > > + hdisplay_max = 8192;
> > > + vdisplay_max = 4320;
> > > + htotal_max = 8192;
> > > + vtotal_max = 8192;
> >
> > I wonder if we can safely bump these before we get the joiner stuff sorted.
> > Hmm. I guess it should be fine as the limit that is supposed to overcome
> > is caused by the cdclk max frequency being too low to allow a single
> > pipe to push enough pixels. And since we check that in .mode_valid() we
> > shouldn't accidentally start to advertize support for modes we can't do.
>
> Yes the intel_dp_mode_valid() will still reject the modes until we have the support
> for big joiner, so allowing these limits should be fine here.
>
> Same for the plane size limits. Plane size limits bumping up is also
> needed in case of tiled 8K display with transcdoer port sync
>
> >
> > Which means these limits should actually be higher than this. 16k for
> > htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe.
>
> Where do we set htotal+hdisplay? And I added this for tgl, since we would be
> supporting the 8K res only on tgl onwards, correct?
We can do 8k on earlier platforms too, assuming the clock is low enough.
Also icl already can do the joining stuff no?
Anwyays these number are just the straight up transcoder max timings
from the spec, and that's what I think they should stay. If we need to
impose some other arbitrary limits for other reasons we should do that
separately.
Hmm. I guess planes is the other thing that's a problem for 8k and such.
The documented max width is too small for any single plane to cover
such a big pipe. We should perhaps be validating modes against the plane
limits as well...
--
Ville Syrjälä
Intel
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