== Series Details == Series: Initial support for Tiger Lake (rev3) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5c5e5e6008d1 drm/i915: Add 4th pipe and transcoder 0cd4b6f0f2d1 drm/i915/tgl: add initial Tiger Lake definitions 777a2d8d8266 drm/i915/tgl: Introduce Tiger Lake PCH cb543d474e7a drm/i915/tgl: Add TGL PCH detection in virtualized environment 9b52a5d4d480 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked 8e56a0e4bf92 x86/gpu: add TGL stolen memory support 7ad31e8ccdb5 drm/i915/tgl: Check if pipe D is fused 52cd60dca858 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A 228a055462e0 drm/i915/tgl: Add power well support f5175d7ae1c3 drm/i915/tgl: Add power well to support 4th pipe 45b62a9eac96 drm/i915/tgl: Add new pll ids 91b16ba0eb18 drm/i915/tgl: Add pll manager 5e768170eebe drm/i915/tgl: Add additional ports for Tiger Lake 7787733b30b1 drm/i915/tgl: update ddi/tc clock_off bits -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \ + (port) + 10)) -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 2 checks, 14 lines checked 5ff6a19fe86f drm/i915/tgl: Add gmbus gpio pin to port mapping 93b16ee61a60 drm/i915/tgl: port to ddc pin mapping e7d46091155c drm/i915/tgl: select correct bit for port select 17b3e3c96fb6 drm/i915/tgl: extend intel_port_is_combophy/tc 33cbf7793050 drm/i915/tgl: init ddi port A-C for Tiger Lake 414c3ae9ddfd drm/i915/tgl: Add vbt value mapping for DDC Bus pin 9bb0ad3b4017 drm/i915/tgl: apply Display WA #1178 to fix type C dongles cd3414367161 drm/i915/gen12: MBUS B credit change a840d06f8c92 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization cf688295aed2 drm/i915/tgl: Add DPLL registers 281d1bcfc226 drm/i915/tgl: Update DPLL clock reference register _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
