On Wed, Jul 03, 2019 at 04:37:34PM -0700, Matt Roper wrote:
> Convert the code that operates directly on gen11 combo PHY's to use the
> new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
> ICL_DPHY_CHKN.
>
> Note that a lot of the PHY programming happens in the MIPI DSI code.
> For clarity I've added a for_each_dsi_phy() to loop over the phys used
> by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so
> it doesn't actually matter which form we use in the DSI code. I've used
> the phy iterator in code that's explicitly working with the combo PHY,
> but left the rest of the DSI code using the port iterator and namespace
> to minimize patch deltas. We can switch the rest of the DSI code over
> to use phy terminology later if this winds up being too confusing.
>
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++--------
> .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++---------
> .../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> .../drm/i915/display/intel_display_power.c | 16 +-
> drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
> drivers/gpu/drm/i915/i915_reg.h | 74 ++++-----
> 8 files changed, 213 insertions(+), 211 deletions(-)
>
<snip>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d53285fb883f..8a4a57ef82a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -268,6 +268,10 @@ enum phy {
> for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
> for_each_if((__ports_mask) & BIT(__port))
>
> +#define for_each_phy_masked(__phy, __phys_mask) \
> + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
> + for_each_if((__phys_mask) & BIT(__phy))
> +
> #define for_each_crtc(dev, crtc) \
> list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c19b958461ca..64627c117c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -395,7 +395,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>
> static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> @@ -403,21 +403,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> /* Display WA #1178: icl */
> if (IS_ICELAKE(dev_priv) &&
> pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> - !intel_bios_is_port_edp(dev_priv, port)) {
> + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
We don't need this on ehl?
Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
> @@ -430,11 +430,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
> index 6d20434636cd..1cd24bd46518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -49,8 +49,11 @@ struct intel_dsi {
>
> struct intel_connector *attached_connector;
>
> - /* bit mask of ports being driven */
> - u16 ports;
> + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
> + union {
> + u16 ports; /* VLV DSI */
> + u16 phys; /* ICL DSI */
> + };
>
> /* if true, use HS mode, otherwise LP */
> bool hs;
> @@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
> return container_of(h, struct intel_dsi_host, base);
> }
>
> -#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_port(__port, __ports_mask) \
> + for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_phy(__phy, __phys_mask) \
> + for_each_phy_masked(__phy, __phys_mask)
>
> static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c9e2e09b6f01..b766ba22045b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,20 +1794,20 @@ enum i915_power_well_id {
> #define _ICL_COMBOPHY_A 0x162000
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x160000
> -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
> +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C)
>
> /* CNL/ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> 4 * (dw))
>
> #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
> +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
> #define CL_POWER_DOWN_ENABLE (1 << 4)
> #define SUS_CLOCK_CONFIG (3 << 0)
>
> -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
> +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
> #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> @@ -1822,23 +1822,23 @@ enum i915_power_well_id {
> #define PWR_DOWN_LN_MASK (0xf << 4)
> #define PWR_DOWN_LN_SHIFT 4
>
> -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
> +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> #define ICL_LANE_ENABLE_AUX (1 << 0)
>
> /* CNL/ICL Port COMP_DW registers */
> #define _ICL_PORT_COMP 0x100
> -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_COMP + 4 * (dw))
>
> #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
> +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
> #define COMP_INIT (1 << 31)
>
> #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
> +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
>
> #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
> +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
> #define PROCESS_INFO_DOT_0 (0 << 26)
> #define PROCESS_INFO_DOT_1 (1 << 26)
> #define PROCESS_INFO_DOT_4 (2 << 26)
> @@ -1850,14 +1850,14 @@ enum i915_power_well_id {
> #define VOLTAGE_INFO_MASK (3 << 24)
> #define VOLTAGE_INFO_SHIFT 24
>
> -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port))
> +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
> #define IREFGEN (1 << 24)
>
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
> +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
>
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
> +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
>
> /* CNL/ICL Port PCS registers */
> #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
> @@ -1870,14 +1870,14 @@ enum i915_power_well_id {
> #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
> #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
> #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
> -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_GRP_AE, \
> _CNL_PORT_PCS_DW1_GRP_B, \
> _CNL_PORT_PCS_DW1_GRP_C, \
> _CNL_PORT_PCS_DW1_GRP_D, \
> _CNL_PORT_PCS_DW1_GRP_AE, \
> _CNL_PORT_PCS_DW1_GRP_F))
> -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_LN0_AE, \
> _CNL_PORT_PCS_DW1_LN0_B, \
> _CNL_PORT_PCS_DW1_LN0_C, \
> @@ -1888,15 +1888,15 @@ enum i915_power_well_id {
> #define _ICL_PORT_PCS_AUX 0x300
> #define _ICL_PORT_PCS_GRP 0x600
> #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
> -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_AUX + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_GRP + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
> -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
> -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
> +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> #define COMMON_KEEPER_EN (1 << 26)
> #define LATENCY_OPTIM_MASK (0x3 << 2)
> #define LATENCY_OPTIM_VAL(x) ((x) << 2)
> @@ -1933,18 +1933,18 @@ enum i915_power_well_id {
> #define _ICL_PORT_TX_GRP 0x680
> #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
>
> -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_AUX + 4 * (dw))
> -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_GRP + 4 * (dw))
> -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_LN(ln) + 4 * (dw))
>
> #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
> -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
> -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
> -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
> +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
> +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> #define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> @@ -1961,10 +1961,10 @@ enum i915_power_well_id {
> #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
> ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> _CNL_PORT_TX_DW4_LN0_AE)))
> -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
> -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
> -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
> -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
> +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
> +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
> +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> #define POST_CURSOR_1_MASK (0x3F << 12)
> @@ -1975,9 +1975,9 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
> -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
> -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
> -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
> +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
> +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> #define TX_TRAINING_EN (1 << 31)
> #define TAP2_DISABLE (1 << 30)
> #define TAP3_DISABLE (1 << 29)
> @@ -1988,10 +1988,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
> -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
> +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
> +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> --
> 2.17.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
