On Thu, Jun 06, 2019 at 03:42:10PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> When SAGV is forced to disabled/min/med/max in the BIOS pcode will
> only hand us a single QGV point instead of the normal three. Fix
> the code to deal with that instead declaring the bandwidth limit
> to be 0 MB/s (and thus preventing any planes from being enabled).
>
> Also shrink the max_bw sturct a bit while at it, and change the
> deratedbw type to unsigned since the code returns the bw as
> an unsigned int.
>
> Since we now keep track of how many qgv points we got from pcode
> we can drop the earlier check added for the "pcode doesn't
> support the memory subsystem query" case.
>
> Cc: felix.j.degrood@xxxxxxxxx
> Cc: Mark Janes <mark.a.janes@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
This one slipped through the cracks, but it looks correct.
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
You'll need to re-spin the patch since intel_bw.c is under the display/
folder now and enough time has passed that we probably want another CI
run anyway.
Matt
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/intel_bw.c | 15 ++++++++++-----
> 2 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 89bf1e34feaa..f4c7afebfa27 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1738,8 +1738,9 @@ struct drm_i915_private {
> } dram_info;
>
> struct intel_bw_info {
> - int num_planes;
> - int deratedbw[3];
> + unsigned int deratedbw[3]; /* for each QGV point */
> + u8 num_qgv_points;
> + u8 num_planes;
> } max_bw[6];
>
> struct drm_private_obj bw_obj;
> diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
> index 753ac3165061..7b908e10d32e 100644
> --- a/drivers/gpu/drm/i915/intel_bw.c
> +++ b/drivers/gpu/drm/i915/intel_bw.c
> @@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
> clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
> bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
>
> + bi->num_qgv_points = qi.num_points;
> +
> for (j = 0; j < qi.num_points; j++) {
> const struct intel_qgv_point *sp = &qi.points[j];
> int ct, bw;
> @@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
> bi->deratedbw[j] = min(maxdebw,
> bw * 9 / 10); /* 90% */
>
> - DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
> + DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> i, j, bi->num_planes, bi->deratedbw[j]);
> }
>
> @@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
> {
> int i;
>
> - /* Did we initialize the bw limits successfully? */
> - if (dev_priv->max_bw[0].num_planes == 0)
> - return UINT_MAX;
> -
> for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> const struct intel_bw_info *bi =
> &dev_priv->max_bw[i];
>
> + /*
> + * Pcode will not expose all QGV points when
> + * SAGV is forced to off/min/med/max.
> + */
> + if (qgv_point >= bi->num_qgv_points)
> + return UINT_MAX;
> +
> if (num_planes >= bi->num_planes)
> return bi->deratedbw[qgv_point];
> }
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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