== Series Details == Series: DSB enablement. URL : https://patchwork.freedesktop.org/series/63013/ State : warning == Summary == $ dim checkpatch origin/drm-tip d1b2b4d2b22b drm/i915/dsb: feature flag added for display state buffer. f910e626c852 drm/i915/dsb: DSB context creation. -:55: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #55: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 120 lines checked 208d2a783e08 drm/i915/dsb: single register write function for DSB. efc2e0d931ee drm/i915/dsb: Added enum for reg write capability. 080a458a7c02 drm/i915/dsb: Indexed register write function for DSB. d3e8201962eb drm/i915/dsb: Update i915_write to call dsb-write. -:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721: +#define I915_WRITE(reg__, val__) \ + (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \ + __I915_REG_OP(write, dev_priv, (reg__), (val__)) -:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg__' - possible side-effects? #42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721: +#define I915_WRITE(reg__, val__) \ + (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \ + __I915_REG_OP(write, dev_priv, (reg__), (val__)) -:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val__' - possible side-effects? #42: FILE: drivers/gpu/drm/i915/i915_drv.h:2721: +#define I915_WRITE(reg__, val__) \ + (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \ + __I915_REG_OP(write, dev_priv, (reg__), (val__)) total: 1 errors, 0 warnings, 2 checks, 26 lines checked aa9a108cf7a9 drm/i915/dsb: Register definition of DSB registers. 5f19d6c09a08 drm/i915/dsb: Check DSB engine status. 905948da193a drm/i915/dsb: functions to enable/disable DSB engine. 531a3721623a drm/i915/dsb: function to trigger workload execution of DSB. 6c5b6c287545 drm/i915/dsb: function to destroy DSB context. ce2dd71592dd drm/i915/dsb: Early prepare of dsb context. f102c82be397 drm/i915/dsb: Cleanup of DSB context. e96046cb8f4f drm/i915/dsb: Documentation for DSB. 5fcaa6842b63 drm/i915/dsb: Enable gamma lut programming using DSB. -:66: WARNING:LONG_LINE: line over 100 characters #66: FILE: drivers/gpu/drm/i915/i915_reg.h:10194: +#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4, \ -:68: WARNING:LONG_LINE: line over 100 characters #68: FILE: drivers/gpu/drm/i915/i915_reg.h:10196: +#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4, \ -:70: WARNING:LONG_LINE: line over 100 characters #70: FILE: drivers/gpu/drm/i915/i915_reg.h:10198: +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4, \ total: 0 errors, 3 warnings, 0 checks, 62 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
