Addressed few review comment provided by Imre on internal mailing list. This series requires Tigerlake platform enablement patches and TGL PSR patches to be merged first, so few patches has commented out original code, which has commented out in order to build the series. DC3CO DMC f/w entry/exit sequence: HSD: https://hsdes.intel.com/appstore/article/#/1405906487 has attached a DC3CO HAS document, HAS document page no.8 has described the DC3CO DMC entry and exit sequence. I am able to validate that DC3CO counter increments on pipe2d emulator. DC5 counter also increment post DC3CO. DC3CO requirements: *Audio codec idle and disabled. *External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled. *Backlight cannot be driven from the display utility pin. It can be driven from the south display. *This feature should be enabled only in Display Video playback on eDP. *DC5 and DC6 not allowed when this feature is enabled. *PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b) *Disable DC3co before mode set, or other Aux, PLL, and DBUF programming, and do not re-enable until after that programming is completed. *DC3co must not be enabled until after PSR2 is enabled. *DC3co must be disabled before PSR2 is disabled. B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196 Anshuman Gupta (10): drm/i915/tgl:Added DC3CO required register and bits. i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask. i915:Added DC3CO power well. drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6. drm/i915/tgl:Added helper function to prefer dc3co over dc5. drm/i915/tgl:Added VIDEO power domain. drm/i915/tgl:DC3CO PSR2 helper. drm/i915/tgl:switch between dc3co and dc5 based on display idleness. drm/i915/tgl:Added DC3CO counter in i915_dmc_info. drm/i915/tgl: Added new DC5/DC6 counter. drivers/gpu/drm/i915/i915_debugfs.c | 23 ++- drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_params.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 13 ++ drivers/gpu/drm/i915/intel_display.c | 45 ++++- drivers/gpu/drm/i915/intel_display.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 55 ++++++ drivers/gpu/drm/i915/intel_psr.h | 2 + drivers/gpu/drm/i915/intel_runtime_pm.c | 228 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_runtime_pm.h | 7 + 12 files changed, 378 insertions(+), 10 deletions(-) -- 2.21.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
