>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of >Lucas De Marchi >Sent: Tuesday, June 25, 2019 10:54 AM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Cc: De Marchi, Lucas <lucas.demarchi@xxxxxxxxx> >Subject: [PATCH 13/28] drm/i915/tgl: Add new pll ids > >From: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> > >Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL changed, >but most registers remained the same, like MGPLL5_ENABLE, MGPLL6_ENABLE. >So continue to use the name from ICL. > >Cc: Madhav Chauhan <madhav.chauhan@xxxxxxxxx> >Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> >Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> >--- > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++++++++++++++---- > 1 file changed, 18 insertions(+), 5 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >index d0570414f3d1..b943f5e3f143 100644 >--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >@@ -110,35 +110,48 @@ enum intel_dpll_id { > > > /** >- * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0 >+ * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 > */ > DPLL_ID_ICL_DPLL0 = 0, > /** >- * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1 >+ * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 > */ > DPLL_ID_ICL_DPLL1 = 1, > /** >- * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL >+ * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL > */ > DPLL_ID_ICL_TBTPLL = 2, > /** >- * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C) >+ * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), >+ * TGL TC PLL 1 port 1 (TC1) > */ > DPLL_ID_ICL_MGPLL1 = 3, > /** > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) >+ * TGL TC PLL 1 port 2 (TC2) > */ > DPLL_ID_ICL_MGPLL2 = 4, > /** > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) >+ * TGL TC PLL 1 port 3 (TC3) > */ > DPLL_ID_ICL_MGPLL3 = 5, > /** > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) >+ * TGL TC PLL 1 port 4 (TC4) > */ > DPLL_ID_ICL_MGPLL4 = 6, >+ /** >+ * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5) >+ */ >+ DPLL_ID_TGL_MGPLL5 = 7, >+ /** >+ * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6) >+ */ >+ DPLL_ID_TGL_MGPLL6 = 8, > }; >-#define I915_NUM_PLLS 7 >+ >+#define I915_NUM_PLLS 9 > > struct intel_dpll_hw_state { > /* i9xx, pch plls */ >-- >2.21.0 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
