On Tue, 25 Jun 2019 18:41:07 +0200, Robert M. Fosha
<robert.m.fosha@xxxxxxxxx> wrote:
Detect GuC firmware load failure due to an exception during execution
in GuC firmware. Output the GuC EIP where exception occurred to dmesg
for GuC debug information.
v2: correct typos, change debug message and error code returned for
GuC exception (Michal)
Signed-off-by: Robert M. Fosha <robert.m.fosha@xxxxxxxxx>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
let's hope it will never show up
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 7 +++++++
drivers/gpu/drm/i915/intel_guc_reg.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 72cdafd9636a..970f39ef248b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -197,6 +197,7 @@ static inline bool guc_ready(struct intel_guc *guc,
u32 *status)
static int guc_wait_ucode(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
u32 status;
int ret;
@@ -216,6 +217,12 @@ static int guc_wait_ucode(struct intel_guc *guc)
ret = -ENOEXEC;
}
+ if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
+ DRM_ERROR("GuC firmware exception. EIP: %#x\n",
+ intel_uncore_read(&i915->uncore, SOFT_SCRATCH(13)));
+ ret = -ENXIO;
+ }
+
if (ret == 0 && !guc_xfer_completed(guc, &status)) {
DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
status);
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index a214f8b71929..d90b88fadb5e 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -37,6 +37,7 @@
#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
#define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
#define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
+#define GS_UKERNEL_EXCEPTION (0x70 << GS_UKERNEL_SHIFT)
#define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
#define GS_MIA_SHIFT 16
#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
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