Quoting Tvrtko Ursulin (2019-06-19 12:04:08) > > On 18/06/2019 12:07, Chris Wilson wrote: > > The process_csb routine from execlists_submission is incompatible with > > the GuC backend. Add a warning to detect if we accidentally end up in > > the wrong spot. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > > Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx> > > Cc: Michał Winiarski <michal.winiarski@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index c400c66d0ee5..bbe6ece9b010 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -1169,6 +1169,7 @@ static void process_csb(struct intel_engine_cs *engine) > > u8 head, tail; > > > > lockdep_assert_held(&engine->active.lock); > > + GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915)); > > > > /* > > * Note that csb_write, csb_status may be either in HWSP or mmio. > > > > I assume it somehow and somewhere happened or you wouldn't be adding the > assert? I've seen a bug (the execlists-only preemption timer firing on icl-guc) that would only be explained by it happening and so wanted to catch it in the act and hopefully find out where we managed to slip up. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
