> -----Original Message-----
> From: Kulkarni, Vandita
> Sent: Wednesday, June 19, 2019 10:49 AM
> To: José Roberto de Souza <jose.souza@xxxxxxxxx>; intel-
> gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>
> Subject: RE: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > José Roberto de Souza
> > Sent: Wednesday, June 19, 2019 1:30 AM
> > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>
> > Subject: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI
> > strap
> >
> > The other additional step in the DSI sequqence for EHL.
A correction in "sequence" will be needed though.
Thanks,
Vandita
> >
> > BSpec: 20597
> > Cc: Uma Shankar <uma.shankar@xxxxxxxxx>
> > Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > ---
> Looks good to me.
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
>
> Thanks.
> Vandita
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ee85428b309f..3a601c739fc6 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct
> > intel_encoder *encoder)
> > I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> > }
> > }
> > +
> > + if (IS_ELKHARTLAKE(dev_priv)) {
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(ICL_DPHY_CHKN(port));
> > + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> > + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> > + }
> > + }
> > }
> >
> > static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) diff
> > --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index
> > 1f2c3ebdf87b..dc7b34cf8b42 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> > #define N_SCALAR(x) ((x) << 24)
> > #define N_SCALAR_MASK (0x7F << 24)
> >
> > +#define _ICL_DPHY_CHKN_REG 0x194
> > +#define ICL_DPHY_CHKN(port)
> > _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> > +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> > +
> > #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
> > (ln0p1)))
> >
> > --
> > 2.22.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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