On Tue, Jun 18, 2019 at 02:44:00PM +0300, Ville Syrjälä wrote: > On Tue, Jun 18, 2019 at 11:16:41AM +0200, Maarten Lankhorst wrote: > > Op 17-06-2019 om 14:34 schreef Ville Syrjälä: > > > On Fri, Jun 14, 2019 at 12:39:41PM +0200, Maarten Lankhorst wrote: > > >> When a planar YUV plane is configured, but the crtc is > > >> marked inactive, we can end up with a linked plane without > > >> visibility. > > > How is that possible? I don't think we should be adding the slave plane > > > if the master is not visible. > > > > > > DPMS off, we calculate the various fields as if the CRTC is on, then disable visibility. > > > > crtc_state->nv12_planes etc still get set, so it works as if the crtc is on. > > > > It's a way of not allowing an invalid result when dpms is off, then breaking on crtc enable. > > Hmm. I wonder when we started to do that. If we're already doing this > much then I wonder how far we are from just dealing with the FIXME in > intel_wm_plane_visible() instead? Still far I guess. Would potentially need to do some surgery on the pipe ddb allocation as well. This whole thing is a bit borked. We clear active_planes but still use it when allocating the Y plane. Hence dpms on could just fail anyway due to not having a free Y plane (as well as due to insufficient watermarks). So if we want to make the Y plane allocation robust I guess we would also need to move clearing the plane visibility to happen after the crtc .atomic_check(). -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
