Quoting John Harrison (2019-06-14 19:17:25) > On 6/14/2019 10:19, Tvrtko Ursulin wrote: > > > > Read-back of 0x20ec (GEN9_CS_DEBUG_MODE1) seems to be causing issues. > > It could be put on the wo_register list if appropriate. And/or made > > RING_FORCE_TO_NONPRIV_RW. > > > > However now I realize that handling of new whitelisting modes is > > missing from the selftest altogether. All RING_FORCE_TO_NONPRIV_RD and > > RING_FORCE_TO_NONPRIV_WR probably need explicit handling there - first > > ones to check they cannot be written to, and skip read-back on the > > second one. > > > > Regards, > > > > Tvrtko > > It looks like there are multiple issues. > > I think the quickest/simplest option right now is to drop a bunch of the > ICL updates (because there are too many for the current 12 slot maximum) > and to drop the problematic CFL updates. > > The only changes that are urgently needed are the HUC status registers. > Unfortunately, they are read-only entries. So the self-test will need to > be updated to cope with those. Not sure what it can do though. Do we > just skip read-only entries? The test can't know what a valid value to > read back is. There's an exception list [wo_register] for registers that don't conform to the test expectations. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
