On Wed, 2 May 2012 22:55:45 -0300, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> intel_wait_for_vblank uses PIPESTAT, which does not exist on Ironlake
> and newer.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 613f871..a2617b2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -806,6 +806,32 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
> return true;
> }
>
> +static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 vblank_start, line;
> + u32 dsl_reg = PIPEDSL(pipe);
> + u32 pipeconf = I915_READ(PIPECONF(pipe));
> +
> + if (!((pipeconf & PIPECONF_ENABLE) &&
> + (pipeconf & I965_PIPECONF_ACTIVE)))
> + return;
> +
> + vblank_start = I915_READ(VBLANK(pipe)) & 0x1FFF;
> +
> + if (pipeconf & PIPECONF_INTERLACE_MASK)
> + vblank_start >>= 1;
> +
> + line = I915_READ(dsl_reg) & DSL_LINEMASK_GEN3;
> +
> + if (line >= vblank_start)
> + return;
The caller expects for at least 1 frame to have passed, the
documentation tends to refer to the registers being latched until the
next vblank. As we don't know precisely when those registers are copied,
we need to wait one complete cycle to be sure that we don't return too
early.
Or maybe I'm being too paranoid. Actually, with modesetting one can
never be too paranoid.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
