From: Paulo Zanoni <paulo.r.zanoni at intel.com>
intel_wait_for_vblank uses PIPESTAT, which does not exist on Ironlake
and newer.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 613f871..a2617b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -806,6 +806,32 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
return true;
}
+static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 vblank_start, line;
+ u32 dsl_reg = PIPEDSL(pipe);
+ u32 pipeconf = I915_READ(PIPECONF(pipe));
+
+ if (!((pipeconf & PIPECONF_ENABLE) &&
+ (pipeconf & I965_PIPECONF_ACTIVE)))
+ return;
+
+ vblank_start = I915_READ(VBLANK(pipe)) & 0x1FFF;
+
+ if (pipeconf & PIPECONF_INTERLACE_MASK)
+ vblank_start >>= 1;
+
+ line = I915_READ(dsl_reg) & DSL_LINEMASK_GEN3;
+
+ if (line >= vblank_start)
+ return;
+
+ if (wait_for_atomic_us((I915_READ_NOTRACE(dsl_reg) &
+ DSL_LINEMASK_GEN3) >= vblank_start, 50000))
+ DRM_DEBUG_KMS("vblank wait timed out\n");
+}
+
/**
* intel_wait_for_vblank - wait for vblank on a given pipe
* @dev: drm device
@@ -819,6 +845,11 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipestat_reg = PIPESTAT(pipe);
+ if (INTEL_INFO(dev)->gen >= 5) {
+ ironlake_wait_for_vblank(dev, pipe);
+ return;
+ }
+
/* Clear existing vblank status. Note this will clear any other
* sticky status fields as well.
*
--
1.7.10
