From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Continuing the conversion and elimination of implicit dev_priv.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 28 ++++++++++++-----------
drivers/gpu/drm/i915/gt/intel_reset.h | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
5 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c0d986db5a75..a046e8dccc96 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
- i915_check_and_clear_faults(i915);
+ i915_check_and_clear_faults(&i915->uncore);
intel_setup_engine_capabilities(i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 60d24110af80..13471916559b 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
-static void clear_error_registers(struct drm_i915_private *i915,
+static void clear_error_registers(struct intel_uncore *uncore,
intel_engine_mask_t engine_mask)
{
- struct intel_uncore *uncore = &i915->uncore;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
u32 eir;
if (!IS_GEN(i915, 2))
@@ -1205,13 +1205,13 @@ static void clear_error_registers(struct drm_i915_private *i915,
}
}
-static void gen6_check_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_faults(struct intel_uncore *uncore)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
u32 fault;
- for_each_engine(engine, dev_priv, id) {
+ for_each_engine(engine, uncore_to_i915(uncore), id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
@@ -1227,16 +1227,16 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
}
}
-static void gen8_check_faults(struct drm_i915_private *dev_priv)
+static void gen8_check_faults(struct intel_uncore *uncore)
{
- u32 fault = I915_READ(GEN8_RING_FAULT_REG);
+ u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
if (fault & RING_FAULT_VALID) {
u32 fault_data0, fault_data1;
u64 fault_addr;
- fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
- fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+ fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
+ fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
@@ -1255,17 +1255,19 @@ static void gen8_check_faults(struct drm_i915_private *dev_priv)
}
}
-void i915_check_and_clear_faults(struct drm_i915_private *i915)
+void i915_check_and_clear_faults(struct intel_uncore *uncore)
{
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
if (INTEL_GEN(i915) >= 8)
- gen8_check_faults(i915);
+ gen8_check_faults(uncore);
else if (INTEL_GEN(i915) >= 6)
- gen6_check_faults(i915);
+ gen6_check_faults(uncore);
else
return;
- clear_error_registers(i915, ALL_ENGINES);
+ clear_error_registers(uncore, ALL_ENGINES);
}
/**
@@ -1316,7 +1318,7 @@ void i915_handle_error(struct drm_i915_private *i915,
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(i915, engine_mask, msg);
- clear_error_registers(i915, engine_mask);
+ clear_error_registers(&i915->uncore, engine_mask);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 580ebdb59eca..d5cf217ba719 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,7 +25,7 @@ void i915_handle_error(struct drm_i915_private *i915,
const char *fmt, ...);
#define I915_ERROR_CAPTURE BIT(0)
-void i915_check_and_clear_faults(struct drm_i915_private *i915);
+void i915_check_and_clear_faults(struct intel_uncore *uncore);
void i915_reset(struct drm_i915_private *i915,
intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 81ff2c78fd55..ee9af4293133 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2340,7 +2340,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_uncore_resume_early(&dev_priv->uncore);
- i915_check_and_clear_faults(dev_priv);
+ i915_check_and_clear_faults(&dev_priv->uncore);
if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2e15850bd987..904cdabc5b64 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2310,7 +2310,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) < 6)
return;
- i915_check_and_clear_faults(dev_priv);
+ i915_check_and_clear_faults(&dev_priv->uncore);
ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
@@ -3588,7 +3588,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_vma *vma, *vn;
- i915_check_and_clear_faults(dev_priv);
+ i915_check_and_clear_faults(&dev_priv->uncore);
mutex_lock(&ggtt->vm.mutex);
--
2.20.1
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