Atm AUX-B transfers can fail with the following error if AUX-A is not enabled: [ 594.594108] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status 0x7c2003ff [ 594.615854] [drm:intel_dp_aux_xfer [i915]] *ERROR* dp aux hw did not signal timeout! [ 594.632851] [drm:intel_dp_aux_xfer [i915]] *ERROR* dp aux hw did not signal timeout! [ 594.632915] [drm:intel_dp_aux_xfer [i915]] *ERROR* dp_aux_ch not done status 0xac2003ff [ 594.641786] ------------[ cut here ]------------ [ 594.641790] dp_aux_ch not started status 0xac2003ff [ 594.641874] WARNING: CPU: 4 PID: 1366 at drivers/gpu/drm/i915/intel_dp.c:1268 intel_dp_aux_xfer+0x232/0x890 [i915] Ville noticed this issue already earlier and managed to work around it by keeping AUX-A always powered whenever AUX-B was used. He also reported the issue to HW folks and they have now root caused the problem and updated BSpec with a fix (see internal BSpec/Index/21257, HSD/1607152412). I noticed the same error - even with the WA being applied - while doing AUX transfers with Chamelium being connected with a DP cable to the source but letting Chamelium imitate an unplug. This is probably some unstandard way on Chamelium's behalf of disconnecting itself from the AUX pins. For instance it could still pull on the AUX pins which would prevent the source from detecting AUX timeouts in the proper way, leading to the ERRORs or WARNs seen in the logs in the Reference: bug below. In case I disconnect the sink properly (the cable itself, not via the Chamelium unplug xmlrpc command) then the AUX timeout signaling works properly and so there won't be any ERRORs/WARNs emitted. Reference: https://bugs.freedesktop.org/show_bug.cgi?id=110718 Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reported-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_combo_phy.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87e8780711d7..bae4a2547eb2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1846,6 +1846,9 @@ enum i915_power_well_id { #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port)) +#define IREFGEN (1 << 24) + #define CNL_PORT_COMP_DW9 _MMIO(0x162124) #define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c b/drivers/gpu/drm/i915/intel_combo_phy.c index 19a9333b727a..98213cc58736 100644 --- a/drivers/gpu/drm/i915/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/intel_combo_phy.c @@ -275,6 +275,12 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) cnl_set_procmon_ref_values(dev_priv, port); + if (port == PORT_A) { + val = I915_READ(ICL_PORT_COMP_DW8(port)); + val |= IREFGEN; + I915_WRITE(ICL_PORT_COMP_DW8(port), val); + } + val = I915_READ(ICL_PORT_COMP_DW0(port)); val |= COMP_INIT; I915_WRITE(ICL_PORT_COMP_DW0(port), val); -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
