On Wed, 15 May 2019, Harish Chegondi <harish.chegondi@xxxxxxxxx> wrote: > display_pipe_crc_irq_handler() skips the first CRC for all GPUs and the > second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT which > is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs. > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Cc: Tomi Sarvela <tomi.p.sarvela@xxxxxxxxx> > Cc: Petri Latvala <petri.latvala@xxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > Signed-off-by: Harish Chegondi <harish.chegondi@xxxxxxxxx> > References: https://bugs.freedesktop.org/show_bug.cgi?id=103191 s/References:/Bugzilla:/ Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_irq.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 233211fde0ea..3809e9f7fae2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1775,11 +1775,11 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > * bonkers. So let's just wait for the next vblank and read > * out the buggy result. > * > - * On GEN8+ sometimes the second CRC is bonkers as well, so > + * On GEN7+ sometimes the second CRC is bonkers as well, so > * don't trust that one either. > */ > if (pipe_crc->skipped <= 0 || > - (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { > + (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) { > pipe_crc->skipped++; > spin_unlock(&pipe_crc->lock); > return; -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
