On Mon, May 06, 2019 at 04:12:50PM +0300, Ville Syrjälä wrote:
> On Mon, May 06, 2019 at 03:35:52PM +0300, Ville Syrjälä wrote:
> > On Fri, May 03, 2019 at 02:26:47AM +0300, Imre Deak wrote:
> > > On ICL we have to make sure that we enable the AUX power domain in a
> > > controlled way (corresponding to the port's actual TypeC mode). Since
> > > the PPS lock - which takes an AUX power ref - is only needed on
> > > eDP/VLV/CHV avoid taking it in other cases.
> > >
> > > Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/intel_dp.c | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index f56cbda59fb3..1ee9b7ebd801 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -6263,6 +6263,10 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> > >
> > > intel_dp->reset_link_params = true;
> > >
> > > + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > > + !intel_dp_is_edp(intel_dp))
> > > + return;
> >
> > vlv/chv need this for all DP ports.
>
> Which is what this does. The wording in the commit message confused me.
Yep, can make it clearer like:
... only needed on eDP on all platforms and eDP/DP on VLV/CHV, ...
> >
> > > +
> > > with_pps_lock(intel_dp, wakeref) {
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> > > --
> > > 2.17.1
> >
> > --
> > Ville Syrjälä
> > Intel
>
> --
> Ville Syrjälä
> Intel
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