On 30/04/2019 11:01, Lisovskiy, Stanislav wrote: > On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote: >> On Tue, 30 Apr 2019, Stanislav Lisovskiy < >> stanislav.lisovskiy@xxxxxxxxx> wrote: >>> Currently due to regression CI machine >>> displays show corrupt picture. >>> Problem is when CDCLK is as low as 79200, picture gets >>> unstable, while DSI and DE pll values were >>> confirmed to be correct. >>> Limiting to 158400 as agreed with Ville. >>> >>> We could not come up with any better solution >>> yet, as PLL divider values both for MIPI(DSI PLL) and >>> CDCLK(DE PLL) are correct, however seems that due to some >>> boundary conditions, when clocking is too low we get >>> wrong timings for DSI display. >>> Similar workaround exists for VLV though, so just >>> took similar condition into use. At least that way >>> GLK platform will start to be usable again, with >>> current drm-tip. >>> >>> v2: Fixed commit subject as suggested. >>> >>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> >>> Acked-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> >> Do we have a bugzilla link? >> >> BR, >> Jani. > > No, or at least I'm not aware of. I just got a machine from CI for > investigation :) I guess it might be worth to create a bug for that. > > > Martin: do we have a bug for CI GLK issue? No idea. Check it out: http://gfx-ci.fi.intel.com/cibuglog-ng/results/knownfailures?query=machine_name+%3D+%27fi-glk-dsi%27+AND+NOT+status_name+%3D+%27skip%27 This possibly could explain all the CRC mismatches we get on GLK-dsi? Time will tell. Martin > > -Stanislav > >> >> >>> --- >>> drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++ >>> 1 file changed, 9 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c >>> b/drivers/gpu/drm/i915/intel_cdclk.c >>> index ae40a8679314..2b23f8500362 100644 >>> --- a/drivers/gpu/drm/i915/intel_cdclk.c >>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c >>> @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const >>> struct intel_crtc_state *crtc_state) >>> IS_VALLEYVIEW(dev_priv)) >>> min_cdclk = max(320000, min_cdclk); >>> >>> + /* >>> + * On Geminilake once the CDCLK gets as low as 79200 >>> + * picture gets unstable, despite that values are >>> + * correct for DSI PLL and DE PLL. >>> + */ >>> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && >>> + IS_GEMINILAKE(dev_priv)) >>> + min_cdclk = max(158400, min_cdclk); >>> + >>> if (min_cdclk > dev_priv->max_cdclk_freq) { >>> DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d >>> kHz)\n", >>> min_cdclk, dev_priv->max_cdclk_freq); >> >> > --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
