On Fri, 26 Apr 2019, Shashank Sharma <shashank.sharma@xxxxxxxxx> wrote:
> From: Uma Shankar <uma.shankar@xxxxxxxxx>
>
> Add macros to define multi segmented gamma registers
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74824f0b5b1..fc50e85ca895 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7198,6 +7198,7 @@ enum {
> #define GAMMA_MODE_MODE_10BIT (1 << 0)
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
> +#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
>
> /* DMC/CSR */
> #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
> @@ -10144,6 +10145,22 @@ enum skl_power_gate {
> #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
> #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
>
> +/* Add registers for Gen11 Multi Segmented Gamma Mode */
> +#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
> +#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
> +#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15)
> +#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0)
See REG_BIT() and REG_FIELD_PREP() at the top of the file.
BR,
Jani.
> +
> +#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
> +#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
> +
> +#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
> + _PAL_PREC_MULTI_SEG_INDEX_A, \
> + _PAL_PREC_MULTI_SEG_INDEX_B)
> +#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
> + _PAL_PREC_MULTI_SEG_DATA_A, \
> + _PAL_PREC_MULTI_SEG_DATA_B)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
Jani Nikula, Intel Open Source Graphics Center
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