== Series Details == Series: i915 vgpu PV to improve vgpu performance URL : https://patchwork.freedesktop.org/series/60055/ State : warning == Summary == $ dim checkpatch origin/drm-tip e9d42b5a1769 drm/i915: introduced vgpu pv capability -:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #89: FILE: drivers/gpu/drm/i915/i915_vgpu.c:89: + DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n", + dev_priv->vgpu.pv_caps); total: 0 errors, 0 warnings, 1 checks, 100 lines checked b94a67da69f3 drm/i915: vgpu shared memory setup for pv optimization -:40: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #40: FILE: drivers/gpu/drm/i915/i915_drv.h:1244: + spinlock_t shared_page_lock[I915_NUM_ENGINES]; -:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #112: FILE: drivers/gpu/drm/i915/i915_vgpu.c:317: + __raw_uncore_write32(uncore, vgtif_reg(g2v_notify), + VGT_G2V_SHARED_PAGE_SETUP); total: 0 errors, 0 warnings, 2 checks, 111 lines checked 1c7ac98d612e drm/i915: vgpu ppgtt update pv optimization -:40: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line #40: FILE: drivers/gpu/drm/i915/i915_gem.c:4474: + if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) + || intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE)) -:54: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #54: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:926: +void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, u64 start, u64 length) -:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #63: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1165: +void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, struct i915_vma *vma, -:72: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #72: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1447: +int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, u64 start, u64 length) -:94: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #94: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:628: +void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, + u64 start, u64 length); -:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #96: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:630: +void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, + struct i915_vma *vma, -:99: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #99: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:633: +int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, + u64 start, u64 length); -:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #137: FILE: drivers/gpu/drm/i915/i915_vgpu.c:296: +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm, + u64 start, u64 length) -:156: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #156: FILE: drivers/gpu/drm/i915/i915_vgpu.c:315: +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm, + struct i915_vma *vma, -:175: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #175: FILE: drivers/gpu/drm/i915/i915_vgpu.c:334: +static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm, + u64 start, u64 length) -:202: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #202: FILE: drivers/gpu/drm/i915/i915_vgpu.c:361: +void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap, void *data) -:244: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #244: FILE: drivers/gpu/drm/i915/i915_vgpu.h:80: +intel_vgpu_enabled_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap) -:247: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line #247: FILE: drivers/gpu/drm/i915/i915_vgpu.h:83: + return intel_vgpu_active(dev_priv) && intel_vgpu_has_pv_caps(dev_priv) + && (dev_priv->vgpu.pv_caps & cap); -:256: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #256: FILE: drivers/gpu/drm/i915/i915_vgpu.h:92: +void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap, void *data); total: 0 errors, 0 warnings, 14 checks, 193 lines checked 2d58d31cddb2 drm/i915: vgpu context submission pv optimization -:131: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #131: new file mode 100644 -:150: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #150: FILE: drivers/gpu/drm/i915/intel_pv_submission.c:15: + reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); ^ total: 0 errors, 1 warnings, 1 checks, 248 lines checked be2bb4f7c1be drm/i915/gvt: GVTg handle pv_caps PVINFO register 46f201bba5fd drm/i915/gvt: GVTg handle shared_page setup -:49: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #49: FILE: drivers/gpu/drm/i915/gvt/gvt.h:693: +int intel_gvt_read_shared_page(struct intel_vgpu *vgpu, + unsigned int offset, void *buf, unsigned long len); -:122: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #122: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:603: +int intel_gvt_read_shared_page(struct intel_vgpu *vgpu, + unsigned int offset, void *buf, unsigned long len) total: 0 errors, 0 warnings, 2 checks, 96 lines checked 9407b02f3909 drm/i915/gvt: GVTg support ppgtt pv optimization -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/gvt/gtt.c:1815: + gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n", + px_dma(&mm->ppgtt->pml4)); -:111: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #111: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2845: +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]) -:136: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #136: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2870: +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]) -:164: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects? #164: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2898: +#define pml4_addr_end(addr, end) \ +({ unsigned long __boundary = \ + ((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \ + (__boundary < (end)) ? __boundary : (end); \ +}) -:170: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects? #170: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2904: +#define pdp_addr_end(addr, end) \ +({ unsigned long __boundary = \ + ((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \ + (__boundary < (end)) ? __boundary : (end); \ +}) -:176: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects? #176: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2910: +#define pd_addr_end(addr, end) \ +({ unsigned long __boundary = \ + ((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK; \ + (__boundary < (end)) ? __boundary : (end); \ +}) -:189: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #189: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2923: +static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt, + u64 start, u64 end, struct ppgtt_walk *walk) -:202: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #202: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2936: + ret = intel_gvt_hypervisor_read_gpa(vgpu, + (pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift), -:223: CHECK:LINE_SPACING: Please don't use multiple blank lines #223: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2957: + + -:225: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #225: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2959: +static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd, + u64 start, u64 end, struct ppgtt_walk *walk) -:237: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #237: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2971: + ret = intel_gvt_hypervisor_read_gpa(vgpu, + (pd & PAGE_MASK) + (index << -:250: CHECK:LINE_SPACING: Please don't use multiple blank lines #250: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2984: + + -:252: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #252: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2986: +static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp, + u64 start, u64 end, struct ppgtt_walk *walk) -:264: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #264: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2998: + ret = intel_gvt_hypervisor_read_gpa(vgpu, + (pdp & PAGE_MASK) + (index << -:276: CHECK:LINE_SPACING: Please don't use multiple blank lines #276: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3010: + + -:278: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #278: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3012: +static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4, + u64 start, u64 end, struct ppgtt_walk *walk) -:289: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #289: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3023: + ret = intel_gvt_hypervisor_read_gpa(vgpu, + (pml4 & PAGE_MASK) + (index << -:302: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #302: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3036: +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]) -:336: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #336: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3070: + walk.mfns = kmalloc_array(num_pages, + sizeof(unsigned long), GFP_KERNEL); -:396: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #396: FILE: drivers/gpu/drm/i915/gvt/gtt.h:282: +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]); -:399: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #399: FILE: drivers/gpu/drm/i915/gvt/gtt.h:285: +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]); -:402: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #402: FILE: drivers/gpu/drm/i915/gvt/gtt.h:288: +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu, + u64 pdps[]); -:412: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vgpu' - possible side-effects? #412: FILE: drivers/gpu/drm/i915/gvt/gvt.h:56: +#define VGPU_PVCAP(vgpu, cap) \ + ((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \ + && vgpu->shared_page_enabled) -:414: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line #414: FILE: drivers/gpu/drm/i915/gvt/gvt.h:58: + ((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \ + && vgpu->shared_page_enabled) total: 0 errors, 0 warnings, 24 checks, 412 lines checked a890471b0072 drm/i915/gvt: GVTg support context submission pv optimization -:61: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #61: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1720: + if (intel_gvt_read_shared_page(vgpu, pv_elsp_off, &pv_elsp, + I915_NUM_ENGINES * sizeof(struct pv_submission))) -:65: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #65: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1724: + memcpy(&execlist->elsp_dwords.data, pv_elsp[ring_id].descs, + 8 * EXECLIST_MAX_PORTS); total: 0 errors, 0 warnings, 2 checks, 43 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
