On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala
<ville.syrjala@xxxxxxxxxxxxxxx> wrote:
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> When I refactored the code into its own function I accidentally
> misplaced the <<16 shifts for some of the registers causing us
> to lose the blue channel entirely.
>
> We should really find a way to test this...
>
> Cc: Uma Shankar <uma.shankar@xxxxxxxxx>
> Fixes: d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming")
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
+Clint
Does this fix the problem you reported earlier this week?
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_color.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index ca341a9e47e6..9093daabc290 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -173,13 +173,13 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
> I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
> I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
> --
> 2.21.0
>
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--
Lucas De Marchi
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