Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming

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On Fri, Apr 19, 2019 at 10:10:26AM +0300, Imre Deak wrote:
Fix the order of lane, port parameters passed to the register macro.

Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")

Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Cc: Aditya Swarup <aditya.swarup@xxxxxxxxx>
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>


Reviewed-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>

thanks
Lucas De Marchi

---
drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 24f9106efcc6..f181c26f62fd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;
	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
-	i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
	u32 val;
-	int i;
+	int ln;

	if (tc_port == PORT_TC_NONE)
		return;

-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
-		val = I915_READ(mg_regs[i]);
+	for (ln = 0; ln < 2; ln++) {
+		val = I915_READ(MG_DP_MODE(ln, port));
		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
		       MG_DP_MODE_CFG_TRPWR_GATING |
		       MG_DP_MODE_CFG_CLNPWR_GATING |
		       MG_DP_MODE_CFG_DIGPWR_GATING |
		       MG_DP_MODE_CFG_GAONPWR_GATING;
-		I915_WRITE(mg_regs[i], val);
+		I915_WRITE(MG_DP_MODE(ln, port), val);
	}

	val = I915_READ(MG_MISC_SUS0(tc_port));
@@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;
	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
-	i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
	u32 val;
-	int i;
+	int ln;

	if (tc_port == PORT_TC_NONE)
		return;

-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
-		val = I915_READ(mg_regs[i]);
+	for (ln = 0; ln < 2; ln++) {
+		val = I915_READ(MG_DP_MODE(ln, port));
		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
			 MG_DP_MODE_CFG_TRPWR_GATING |
			 MG_DP_MODE_CFG_CLNPWR_GATING |
			 MG_DP_MODE_CFG_DIGPWR_GATING |
			 MG_DP_MODE_CFG_GAONPWR_GATING);
-		I915_WRITE(mg_regs[i], val);
+		I915_WRITE(MG_DP_MODE(ln, port), val);
	}

	val = I915_READ(MG_MISC_SUS0(tc_port));
--
2.13.2

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