Quoting Chris Wilson (2019-04-18 14:07:49)
> Quoting Tvrtko Ursulin (2019-04-18 13:42:59)
> >
> > On 17/04/2019 08:56, Chris Wilson wrote:
> > > -static int init_render_ring(struct intel_engine_cs *engine)
> > > +static int rcs_resume(struct intel_engine_cs *engine)
> > > {
> > > struct drm_i915_private *dev_priv = engine->i915;
> > > - int ret = init_ring_common(engine);
> > > - if (ret)
> > > - return ret;
> > >
> > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> > > if (IS_GEN_RANGE(dev_priv, 4, 6))
> > > @@ -875,7 +875,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> > > if (INTEL_GEN(dev_priv) >= 6)
> > > ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
> > >
> > > - return 0;
> > > + return xcs_resume(engine);
> >
> > This inverts the order between the common and rcs init. One thing which
> > jump out is the RING_IMR which is now done after starting the engine.
> > Can we lose an interrupt now?
>
> That write shouldn't be there, we take care of that inside the restart.
Even more to the point, they should have been set before we started the
engine!
Eeek, that looks to be really funky old behaviour.
-Chris
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