With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de1ba19..c225de4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1198,6 +1198,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
POSTING_READ(reg);
}
+/* SBI access */
+static inline void
+SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value)
+{
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_DATA,
+ value);
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_READY |
+ SBI_CTL_OP_CRWR);
+
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
+}
+
+static inline u32
+SBI_READ(struct drm_i915_private *dev_priv, u16 reg)
+{
+ u32 value;
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_READY |
+ SBI_CTL_OP_CRRD);
+
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
+
+ value = I915_READ(SBI_DATA);
+
+ return value;
+}
+
/**
* intel_enable_pch_pll - enable PCH PLL
* @dev_priv: i915 private structure
--
1.7.9.2
