On Fri, Apr 12, 2019 at 12:27:46PM -0700, Souza, Jose wrote:
> On Fri, 2019-04-12 at 11:09 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > v2: - Rename commit (Jose)
> > - Include a wm workaround (Jose and Lucas)
> > - Include display core init (Jose and Lucas)
> > v3: Add a missing case of gen greater-than 11 (Jose)
>
> This is shining now
pushed, thanks
>
> >
> > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8e826a6ab62e..7357bddf9ad9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> > memset(&wm->wm[level], 0, sizeof(wm-
> > >wm[level]));
> >
> > /*
> > - * Wa_1408961008:icl
> > + * Wa_1408961008:icl, ehl
> > * Underruns with WM1+ disabled
> > */
> > - if (IS_ICELAKE(dev_priv) &&
> > + if (IS_GEN(dev_priv, 11) &&
> > level == 1 && wm->wm[0].plane_en) {
> > wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_init_clock_gating_hooks(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (IS_ICELAKE(dev_priv))
> > + if (IS_GEN(dev_priv, 11))
> > dev_priv->display.init_clock_gating =
> > icl_init_clock_gating;
> > else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > cnl_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 3107a742d8ad..d4f4262d0fee 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> > * The enabling order will be from lower to higher indexed
> > wells,
> > * the disabling order is reversed.
> > */
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (IS_GEN(dev_priv, 11)) {
> > err = set_power_wells(power_domains, icl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, cnl_power_wells);
> > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> > drm_i915_private *i915, bool resume)
> >
> > power_domains->initializing = true;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (INTEL_GEN(i915) >= 11) {
> > icl_display_core_init(i915, resume);
> > } else if (IS_CANNONLAKE(i915)) {
> > cnl_display_core_init(i915, resume);
> > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> > drm_i915_private *i915,
> > intel_power_domains_verify_state(i915);
> > }
> >
> > - if (IS_ICELAKE(i915))
> > + if (INTEL_GEN(i915) >= 11)
> > icl_display_core_uninit(i915);
> > else if (IS_CANNONLAKE(i915))
> > cnl_display_core_uninit(i915);
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index a04dbc58ec1c..c0977036db79 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(wal, "context");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_ctx_workarounds_init(engine);
> > else if (IS_CANNONLAKE(i915))
> > cnl_ctx_workarounds_init(engine);
> > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> > *i915, struct i915_wa_list *wal)
> > static void
> > gt_init_workarounds(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_gt_workarounds_init(i915, wal);
> > else if (IS_CANNONLAKE(i915))
> > cnl_gt_workarounds_init(i915, wal);
> > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(w, "whitelist");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_whitelist_build(w);
> > else if (IS_CANNONLAKE(i915))
> > cnl_whitelist_build(w);
> > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (IS_GEN(i915, 11)) {
> > /* This is not an Wa. Enable for better image quality
> > */
> > wa_masked_en(wal,
> > _3D_CHICKEN3,
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